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A B C D E
W3V/A SCHEMATIC V2.1
1
PAGE Content PAGE Content 1
SYSTEM PAGE REF. POWER PAGE REF.
4 DOTHAN CPU-1
5 DOTHAN CPU-2 49 VCORE_MAX1987
6 CPU CAP/THERMAL SENSOR/ITP 50 SYSTEM
7 ALVISO: CPU 51 1.5V,1.8V,2.5V,1.05V
8 ALVISO: DDR2 & DMI & PEG 52 VGA VCORE
9 ALVISO: DDR2 53 1.5VA & DDR2
10 ALVISO: POWER & Caps 54 PIC16C54/BATCON/PWOK
11 ALVISO: GND & NCTF & Straps 55 CHARGER
12 CLOCK GEN (ICS954213) 56 BATLOW/SD#
2 13 DDR2 SODIMM(0) & Caps 57 LOAD SWITCH 2
14 DDR2 SODIMM(1) & Caps 58 BATCON
15 DDR2 TERMINATOR 59 Power Flowchart
16 ATI M24: MAIN 60 HISTORY
17 ATI M24: MEMORY/SS 61 DC_IN CONN.
18 ATI M24: PWR & GND 62 ODD CONN.
19 ATI M24: Strapping 63 TP&LED CONN
20 LVDS/INVERTER
21 CRT/TV/TPM CONN
22 ICH6: SATA/LPC/IDE/ACZ (1)
23 ICH6: PCI/DMI/USB/PCIE(2)
3
24 ICH6M: PWR/GND/CAPS(3) 3
25 ICH6: PULL UP & Straping
26 SATA to PATA BRIDGE
27 HDD CON
28 SWAP BAY CON
29 USB PORTS
30 SUPER I/O (LPC47N207)
31 FIR & FWH
32 KBC 38857
33 Azalia AUDIO (ALC861-VS)
34 AUDIO AMP/JACKS
35 MIC AMP
4
36 SMBUS 4
37 PCI GIGA LAN (88E8001)
38 RJ11_RJ45/MDC/BT
39 MINIPCI
40 PCI CARDBUS (R5C841)
41 PCI PCMCIA SOCKET A
42 IEEE1394A/3in1 CONN
43 LEDs & DEBUG PORT
44 DJ/HOTKEY/TP LED
45 PWR SW/RESET/KBC LED
46 FAN & DC_IN
5
47 POWER-ON SEQUENCE 5
48 DISCHARGE/EMI/VCCA
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REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 1 OF 63 Content & History RELEASE DATE : Alice Shih
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A B C D E
W3V/A:Dothan & Alviso-PM+M24-CSP/Alviso-GM
BLOCK DIAGRAM VCORE
1 49 1
2nd MAIN SYSTEM 50
BATTERY BATTERY
(3S2P) (4S2P)
1.5V,1.8V,
58 58 1.05V,2.5V 51
CHARGE
CPU 55
CAP/RES RESET SM_BUS
TV CONN
21 CLOCK GEN.
Dothan .... 6 45 36
PIC16C54
478 uFCPGA
ICS954213 4,5 54
12
2 LVDS & HOST BUS BATLOW/SD# 2
INVERTER AGTL 1.468V,133MHZ 56
CONN 20
DDR DCIN
DDR2 400/533 CAP/RES LOAD Switch
ATI PCI-E x16
ALVISO
DDR2 SDRAM 400/533MHz SODIMM X2 ... 15
RTC
FAN 46 57
CRT CONN CON.
21
M24/M22 1257 uFCBGA +1.8V
+0.9VS 13,14
VGA VCORE
16,17,18,19 7,8,9,10,11 Thermal 52
Sensor
(MAX6657) 1.5VA,0.9VS
DMI x4 6 53
USB x3 USB2.0 PCI_BUS 3.3V, 33MHz
3
29 ICH6-M 3
IDE_BUS 609 BGA
KEYBOARD COVER FPC
LEDs LID SENSOR
PATA SATA Azalia
SATA to PATA 22,23,24,25
SWAP BRIDGE GIGA LAN MINI-PCI 3-IN-1 CARDBUS
TOUCHPAD BOARD BAY 28 MARVELL TYPEII 39 CARD RICOH
SILICON IMAGE READER
LED FPC TOUCHPAD Sil3811 88E8001 37 42 R5C841 40
26
LEDs
PATA
AUDIO DJ FPC Azalia Azalia LAN IO RJ11+RJ45
HDD CODEC MDC 38 JACK CONN 1394
AUDIO DJ SWITCH 27 38 SLOT CARDBUS
4
ALC861-VS33 CONN. 38 42
4
1 SLOT
AUDIO DJ LED
LPC, 33MHz VCCA, VCCB
VPPA, VPPB
AUDIO AMP 41
HOTKEY FPC TPA0212
34
INSTANT KEYS
SUPER I/O KEYBOARD
DC-IN BOARD SMSC CONTROLLER FWH
47N207 30 M3885XHP 32 31
DC-IN JACK Headphone
34
ODD BOARD
5 FIR INTERNAL MIC AMP 5
ODD CON. KEYBOARD NJM2100 MIC IN
32 35 34
31
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REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 2 OF 63 BLOCK DIAGRAM RELEASE DATE : Alice Shih
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IDSEL# REQ/GNT# Interrupts PC/PCI
Azalia : PCI_INTB#
PCI Device
USB 0,1 : PCI_INTA#
Chipset (Host to PCI) (AD30 internal) n/a USB 2,3 : PCI_INTD#
Mini_PCI AD18 3 B,D USB 4,5 : PCI_INTC#
LAN --88E8001 AD16 0 C
1 1
CardBus AD17 1 B
1394 AD17 1 A SMBUS ADDRESS : CLK = 1101001x ( D2 )
3 IN 1 1 C DDR_SODIMM0 = 1010010x ( A4 )
DDR_SODIMM1 = 1010000x ( A0 )
THERMAL = 1001100x ( 98 )
M38857_GPIO Used_As Signal_Name
P20 GPO KBCRSM
ICH6M_GPIO Used As Signal Name P21 GPO BAT_SEL
GPIO00 GPI KBDDT0 P22 GPO BAT_LEARN
2 GPIO01 GPI KBDDT1 P23 GPO MSK_INSTKEY# 2
GPIO06 GPI PM_BMBUSY# P42 GPO WATCHDOG
GPIO07 GPI FIR_SEL P43 GPI SWDJ_EN#
GPIO08 GPI EXTSMI#_3A P44 GPO KBCPURST_3Q
GPIO11 GPI LID_ICH#_3A P45 GPO KBC_GA20
M38857_GPIO Used_As Signal_Name
GPIO12 GPI KBDSCI_3 P46 GPO KBSCI_3Q
P27 GPO --
GPIO13 GPI ATI_OVERTEMP# P47 GPI PM_CLKRUN#
P26 GPO NUM_LED#
GPIO14 GPI GPI14 P50 GPI BAT_LLOW#_KBC
P25 GPO CAP_LED#
3 3
GPIO15 GPI CHG_EN#_OC P51 GPO DJ_LED_EN
P24 GPO SET_PCIRSTNS#
GPIO16 GPO GPO16 P52 GPO WIRELESS_LED#
P41 GPO BT_LED#
GPIO17 GPO GPO17 P53 GPO BAT_LOW#_KBC
P40 GPO KBC_EXTSMI
GPIO21 GPO BACK_OFF# P54 GPI BAYDOCK_IN#
GPIO23 GPO FWH_WP# P55 GPI BAT1_IN#_OC
GPIO24 GPO CB_SD# P56 GPO FAN_DA 47N207_GPIO Used_As Signal_Name
GPIO25 BLINK ICH6_1HZ P57 GPO ADJ_BL GP10 GPI BAY_IN0
GPIO26 GPI SATA_DET_#0 P60 GPI BT_# GP11 GPI BAY_IN1
4 4
GPIO27 GPI PCB_VID0 P61 GPI INTERNET_# GP12 GPI --
GPIO28 GPI PCB_VID1 P62 GPI CPUFAN_SPD_A GP13 GPI SW_RST#
GPIO29 GPI PCB_VID2 P63 GPI WIRELESS_# GP14 GPIO --
GPIO30 GPI SATA_DET_#2 P64 GPI ACIN_OC GP15 GPO BAY_RST
GPIO31 GPI AGP_EXT P65 GPI MARATHON_# GP16 GPO DJKEY_EN
GPIO33 GPO XIDE_EN#_3 P66 GPO PANLOCK_# GP17 GPO 802_EN#
GPIO34 GPO OP_SD# P67 GPI BAT2_IN#_OC GP34 GPO OVER_CLK1
5 GPIO40 GPI PID0 P76 GPIO SMD_BAT_KBC GP35 GPO OVER_CLK2 5
GPIO41 GPI PID1 P77 GPO SMC_BAT_KBC GP36 GPO --
bom
REVISION Monday, January 17, 2005 SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V
DATE: DESCRIPTION:
SHEET OF SYSTEM INFORMATION RELEASE DATE : M.Y.
2.1 3 63
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5 4 3 2 1
H_D#[63:0] 7
U52B U52A
7 H_A#[16:3]
H_A#16 AA2 N2 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# 7 D[15]# D[47]#
H_A#15 Y3 A10 H_D#14 E23 AA26 H_D#46
A[15]# PRDY# H_BPM#4 6 D[14]# D[46]#
H_A#14 AA3 B10 H_D#13 B23 Y23 H_D#45
A[14]# PREQ# H_BPM#5 6 D[13]# D[45]#
H_A#13 U1 H_D#12 C26 V26 H_D#44
H_A#12 A[13]# H_D#11 D[12]# D[44]# H_D#43
Y1 A[12]# BNR# L1 H_BNR# 7 E24 D[11]# D[43]# U25
H_A#11 Y4 J3 H_D#10 D24 V24 H_D#42
A[11]# BPRI# H_BPRI# 7 D[10]# D[42]#
ADDRESS GROUP 0
DATA GROUP 0
H_A#10 H_D#9 H_D#41
2
W2 A[10]# B24 D[9]# D[41]# U26
H_A#9 T4 H_D#8 C20 AA23 H_D#40
A[9]# D[8]# D[40]#
DATA GROUP
H_A#8 W1 A7 H_D#7 B20 R23 H_D#39
A[8]# DBR# H_DBRESET# 6,22 D[7]# D[39]#
D H_A#7 V2 H_D#6 A21 R26 H_D#38 D
H_A#6 A[7]# H_D#5 D[6]# D[38]# H_D#37
R3 A[6]# B26 D[5]# D[37]# R24
H_A#5 V3 H_D#4 A24 V23 H_D#36
H_A#4 A[5]# H_D#3 D[4]# D[36]# H_D#35
U4 A[4]# DEFER# L4 H_DEFER# 7 B21 D[3]# D[35]# U23
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# 7 D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
7 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 7 D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 REQ[3]# 7 H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 7
H_REQ#2 T2 C23 W25
REQ[2]# 7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7
H_REQ#1 P3 C22 W24
REQ[1]# 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
H_REQ#0 R2 REQ[0]# H_D#31 H_D#63
7 H_REQ#[4:0] N4 H_BR0# 7 K25 AF26
CONTROL
BR0# +VCCP H_D#30 D[31]# D[63]# H_D#62
N25 D[30]# D[62]# AF22
H_D#29 H26 AF25 H_D#61
H_IERR# R738 2 D[29]# D[61]#
IERR# A4 1 56Ohm H_D#28 M25 D[28]# D[60]# AD21 H_D#60
H_D#27 N24 AE21 H_D#59
7 H_A#[31:17] D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
A[31]# D[26]# D[58]#
3
DATA GROUP 1
H_A#30 AE1 B5 H_D#25 J25 AD24 H_D#57
A[30]# INIT# H_INIT# 22 +VCCP D[25]# D[57]#
H_A#29 H_D#24 H_D#56
DATA GROUP
AF3 A[29]# M23 D[24]# D[56]# AF23
H_A#28 AD6 H_D#23 J23 AE22 H_D#55
A[28]# D[23]# D[55]#
ADDRESS GROUP 1
H_A#27 AE2 J2 H_D#22 G24 AD23 H_D#54
A[27]# LOCK# H_LOCK# 7 D[22]# D[54]#
1
H_A#26 AD5 H_D#21 F25 AC25 H_D#53
H_A#25 A[26]# R748 H_D#20 D[21]# D[53]# H_D#52
AC6 A[25]# H24 D[20]# D[52]# AC22
H_A#24 AB4 54.9Ohm H_D#19 M26 AC20 H_D#51
H_A#23 A[24]# 1% H_D#18 D[19]# D[51]# H_D#50
AD2 A[23]# L23 D[18]# D[50]# AB24
H_A#22 AE4 /* H_D#17 G25 AC23 H_D#49
H_A#21 A[22]# H_D#16 D[17]# D[49]# H_D#48
2
AD3 A[21]# RESET# B11 H_CPURST# 6,7 H23 D[16]# D[48]# AB25
H_A#20 AC3 L2 H_RS#2 J26 AD20
A[20]# RS[2]# 7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7
H_A#19 AC7 K1 H_RS#1 K24 AE24
A[19]# RS[1]# 7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7
C H_A#18 AC4 H1 H_RS#0 L24 AE25 C
A[18]# RS[0]# 7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7
H_A#17 AF4 A[17]# H_RS#[2:0] 7
AE5 M3 SOCKET479P
7 H_ADSTB#1 ADSTB[1]# TRDY# H_TRDY# 7
K3 +1.8VS VCCA_+1.5VS_+1.8VS +1.8VS_VCCA
HIT# H_HIT# 7
7 DPWR# C19 DPWR# HITM# K4 H_HITM# 7
R784
1 2 0Ohm R785
1 2 0Ohm /* +1.8VS_VCCA
SOCKET479P /*
R783
1 2 0Ohm R782
1 2 0Ohm
P/N = 12-046004791 /*
+1.8VS_PROC R1.1#1
+1.5VS
1
1
1
1
1
1
1
1
C769 C770 C198 C201 C200 C202 C778 C768
10UF/10V 0.01UF 10UF/10V 0.01UF 10UF/10V 0.01UF 10UF/10V 0.01UF
2
2
2
2
2
2
2
2
U52C
12 CLK_CPU_BCLK B15 BCLK[0]
B14
HOSTCLK
12 CLK_CPU_BCLK# BCLK[1] H_COMP3
1 2 A16 ITP_CLK[0] COMP[3] AB1
R756 1 2 49.9Ohm 1% A15 AB2 H_COMP2 Place near CPU pin
R754 49.9Ohm 1% ITP_CLK[1] COMP[2] H_COMP1
COMP[1] P26
C2 P25 H_COMP0
22 H_A20M# A20M# COMP[0]
22 H_FERR# D3 FERR#
LEGACY CPU
22 H_IGNNE# A3 IGNNE#
Layout note:
22 H_DPSLP# B7 DPSLP# ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo