Service Manuals, User Guides, Schematic Diagrams or docs for : asus z61ae
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5 4 3 2 1
D D
Z61Ae SCHEMATIC V2.0
PAGE Content PAGE Content Notice
SYSTEM PAGE REF. POWER PAGE REF.
01 The Z61Ae project code is ?
4 DOTHAN CPU-1 43 POWER-ON SEQUENCE
5 DOTHAN CPU-2 44 VCORE ADP3205 02 CON17/CON19 are SMT Level(SMT Request);DC Jack J6 is DIP Level.
6 CPU CAP & THERMAL SENSOR 45 SYSTEM CN1/J1/U23 are changed to DIP Level(They will drop in SMT reflow ).
7 ALVISO: CPU 46 2.5V & 1.5V & 1.8V & 1.05V 03 J4 is changed to DIP.Due to it will broken in reflow.
8 ALVISO: DDR2 & DMI & PEG 47 1.5VA & DDR2
9 ALVISO: DDR2 48 PIC16C54/PWROK 04 Need to add ME and Power 59 level BOM in EE 60 BOM
10 ALVISO: POWER & Caps 49 BATCONN
11 ALVISO: GND & NCTF & Straps 50 CHARGER 05 Check FWH IC 05-001017122 in BOM.
12 DDR2 SO-DIMM_0 51 BATLOW/SD# Alviso U49 need to be changed to C1 version 02-010002640 (INTEL
06 ALVISO-GM SL8G2),second source is 02-010002610(C0 version)
13 DDR2 SO-DIMM_1 52 LOAD SWITCH
14 DDR2 ADDRESS TERMINATION 53 +5VLCM AMI BIOS LABEL P/N:15-135001010.
C
07 It need to add in P/R 59-MID BOM by ME.
C
15 LVDS & INVERTER CONNECTOR
16 CRT
08 J2 need to be unmounted at PR stage for ATS power test
17 ICH6M--SATA/LPC/IDE/PM (1)
18 ICH6M--PCI/DMIUSB/PCIE (2) R501(255 ohm) 10G213255013010 need to add second source 10-003412515.
09
19 ICH6M--PWR/GND(3)
20 ICH6M--PULL UP/STRAP (4) Add ACCL PCB Vendor 08-26ZA0020W???-->Need to create in SMT level.
10
21 CLOCK ICS954206 Need add other PCB vendors by document manager.
22 HDD & SWAP BAY CONN All 0.01uF/25V/X7R (P/N:11-034110320) need to add 11-034110323
11
23 USB PORTS into second source.
24 SUPER I/O LPC47N217 MINIPCI Connector (P/N:12-023511240) need to add 12-023521243
25 SCREW HOLE 12 into second source.
26 PORT BAR 3 All CHIP RES. ARRAY 10 OHM(0402) 8R16P (P/N:10-124901000) need
13
27 KBC 38857 to add 10-12490100A into second source.(ECR is NA12958)
28 SM BUS & POWER PORT
14 If delete debug card function,R876 and R628 mount 0 ohm.
29 LAN-RTL8101L
30 RJ45 / RJ11
15 If use another power
31 MINIPCI switch method.D30 unmount.
32 PCI CARDBUS R5C841
16 If use another power
B 33 PCI PCMCIA SOCKET A switch method.C616 B
34 PCI IEEE1394A & 3 IN1 CON mount 0.1uF/0402
35 FAN CONTROL
36 FWH BIOS/Bluetooth Conn.
37 AUDIO CODEC ALC880
38 AUDIO_AMP_MB (TPA0212)
39 MIC AMP & MDC Conn.
40 LED BOARD
41 TP CONN
42 DISCHARGE MOS/EMI
A A
Title : Z61AE PAGE REF.
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 1 of 57
5 4 3 2 1
5 4 3 2 1
Z61Ae: DOTHAN/ALVISO-GM BLOCK DIAGRAM
Main Battery is Li-ION 8 cells(4*2),16.8V(4.2V*4),4400mAH(2200mAH*2),65W(3.7V*4cell*4.4A) battery pack.
Second battery is Li-ION 6 cells(3*2),12.6V(4.2*3),3600mAH(1800mAH*2),40W(3.7V*3 cells*3.6A)battery pack.
BATTERY
2 TYPE SWITCH BOARD CON
CLOCK
D D
GEN. 3 X 2 & FUNCTION KEY LED
ICS954206 4 X 2 TOUCHPAD CONN
PAGE 21 PAGE 49
PAGE 40 PAGE 41
Dothan CPU
POWER
RESET SM_BUS
SCREW DISCHARGE
PAGE 4,5
478 uFCPGA
.... PAGE 6
CAP
SEQENCE
PAGE 43 PAGE 43 PAGE 28
HOLE
PAGE 25
CIRCUIT
PAGE 42
LVDS &
INV. HOST BUS
PAGE 15 AGTL
1.468V,133MHZ
CRT DDR2 400/533 FAN
DDR2 SDRAM 400/533MHz DDR RTC
PAGE 16
CONN
ALVISO
Intel 915GM C1 version
SODIMM X2
+1.8V
.... CAP/RES
CON.
+0.9VS PAGE 13,14 PAGE 35 PAGE 17
TO PORT BAR3 1257 uFCBGA
PAGE 12,13
CONN. SWITCH PAGE 7,8,9,10,11
(FOR CRT) H/W MONITOR
C PAGE 16
THERMAL C
PAGE 26 DMI x4 (ADT7463)
PAGE 35
USB X4 USB2.0 PCI_BUS 3.3V, 33MHz
TO PORT BAR3 PAGE 23 SATA BUS
CONN. PATA BUS ICH6-M AC LINK / ACZ
(FROM USB Intel ICH6 B2 version
PORT2) 3 IN 1 CARD CARDBUS LAN 10/100M MINI PCI
PAGE 26
609 BGA READER RICOH LAN-RTL8101L TYPE III
HDD SATA TO PATA SWAP BAY PAGE 17,18,19,20 (MMC/SD/ R5C841
Master SII3811CNU (HOT PAGE 31
TO BLUETOOTH MS-PRO) PAGE 32,33 PAGE 29
PAGE 22 PAGE 22 PLUG)
PAGE 22
(FROM USB PAGE 34
PORT5)
R1.1-S01 LPC, 33MHz RJ11 JACK
PAGE 31
LAN IO RJ45
Azalia
CARDBUS CONN
PAGE 30
ALC880-H 1 SLOT PAGE 30
1394 VCCA, VCCB
SUPER I/O KEYBOARD PAGE 37
SLOT VPPA, VPPB
CONTROLLER PAGE 34 PAGE 33 SWITCH
LPC47N217 M3885XHP AMI 4MB FLASH AUDIO AMP MDC CONN.
B
PAGE 24 PAGE 27
FWH TPA0212 PAGE 26
B
PAGE 38 PAGE 39
PAGE 36
VCORE
PAGE 44 TO PORT BAR3
TO PORT BAR3 INTERNAL
CONN.
SYSTEM CONN. KEYBOARD SPDIF
(FOR LAN)
PAGE 45 (FOR LPT) PAGE 38 PAGE 26
PAGE 26 PAGE 27
1.5V,1.8V,
MIC AMP
1.05V,2.5V PAGE 46 MIC IN
NJM2100
PAGE 39 PAGE 38
CHARGE
PAGE 50
PIC16C54
BATCON PAGE 48,49
BATLOW/SD# PORT BAR III part number is 90-N6W1P1010
PAGE 51,53
LOAD Switch CON2 PIN1 CON1 PIN1
PAGE 52 PIN2 PIN2
A A
+0.9VS
PAGE 47
PORT BAR 3
DC IN (19V TOP VIEW
DC,3.42A,65W)53
PAGE
CON5 CON4 CON3
CN2 CN3 J1
Title : BLOCK DIAGRAM
CRT USB USB RJ45 LPT DCIN ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 2 of 57
5 4 3 2 1
5 4 3 2 1
***********GPIO setting is not final in this page.*********
***********Please reference Z61Ae GPIO setting document.*********
D
IDSEL# REQ/GNT# Interrupts PC/PCI
Azalia : PCI_INTB# D
PCI Device
USB 0,1 : PCI_INTA#
Chipset (Host to PCI) (AD30 internal) n/a USB 2,3 : PCI_INTD#
Mini_PCI AD18 3 B,D USB 4,5 : PCI_INTC#
LAN-RTL8101L AD16 0 C
CardBus AD17 1 B
1394 AD17 1 A SMBUS ADDRESS : CLK = 1101001x ( D2 )
3 IN 1 1 C DDR_SODIMM0 = 1010010x ( A4 )
DDR_SODIMM1 = 1010000x ( A0 )
ICH6M_GPIO Use As Signal Name Power M38857_GPIO USE_AS SIGNAL_NAME
GPI 00 GPI KBDDT0 P23 GPO M38857_GPIO USE_AS SIGNAL_NAME
GPI 01 GPI KBDDT1
GPI 02 GPI N/A (PIRQE#) P22 GPO BAT_LEARN P27 GPO SCROLLOCK#
GPI 03 GPI N/A (PIRQF#) P21 GPO BAT_SEL P26 GPO NUM_LED#
GPI 04 GPI N/A (PIRQG#)
GPI 05 GPI N/A (PIRQH#) P20 GPO KBCRSM P25 GPO CAP_LED#
GPI 06 GPI BMBUSY# P42 GPO WATCHDOG P24 GPO SET_PCIRSTNS#
C
GPI 07 GPI C
GPI 08 GPI EXT_SMI#_3A P43 GPI CHG_FULL_OC P41 GPO EMAIL_LED#
GPI 09 GPI N/A (USB_OC#4) P44 GPO KBDCPURST_3Q P40 GPO KBC_EXTSMI
GPI 10 GPI N/A (USB_OC#5)
GPI 11 GPI LID_ICH_3A P45 GPO KBC_GA20
GPI 12 GPI KBDSCI_3 P46 GPO KBSCI_3Q R5C593_GPIO USE_AS SIGNAL_NAME
GPI 13 GPI BAT1_LLOW#_ICH6
GPI 14 GPI BAT2_LLOW#_ICH6 P47 GPI PM_CLKRUN# IRQ3 GPO
GPI 15 GPI P50 GPO BAT_LOW#_KBC IRQ4 GPO
GPO 16 GPO
GPO 17 GPO P51 GPO XIDE_EN#_3 IRQ5 GPO
GPO 19 BLINK P52 GPO BAYDOCK_IN# IRQ7 GPO
GPO 21 GPO BACK_OFF#
GPO 23 GPO FWH_WP# P53 GPO BT_ON
GPIO24 GPO CB_SD# P54 GPI BAY_RST
GPIO25 GPO IHZ_ICH6
GPI 26 GPI P55 GPI BAT1_IN#_OC
GPIO27 GPI PCB_VID0 P56 GPO 47N217_GPIO USE_AS SIGNAL_NAME
GPIO28 GPI PCB_VID1
B B
GPI 29 GPI PCB_VID2 P57 GPO ADJ_BL GPI23 GPI
GPI 30 GPI P67 GPI BAT2_IN#_OC GPI40 GPI PID_0
GPI 31 GPI ACIN_OC_3
GPIO33 GPO P66 GPI DISTP# GPI41 GPI PID_1
GPIO34 GPO OP_SD# P65 GPI MARATHON_# GPI42 GPI
GPI 40 GPI PCB_VID3
GPI 41 GPI BATSEL_2P P64 GPI ACIN_OC GPI43 GPI
GPO 48 GPO P63 GPI LID_ICH#_3 GPI44 GPI BAY_IN0
GPO 49 GPO N/A (CPUPWRGD)
P62 GPI 802_ON GPI45 GPI BAY_IN1
P61 GPI INTERNET# GPI46 GPO
P60 GPI EMAIL# GPI47 GPO
P76 GPIO SMD_BAT
P77 GPIO SMC_BAT
A A
Title : Schematic information
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 3 of 57
5 4 3 2 1
5 4 3 2 1
CPU Socket P/N : 12-046004791
H_D#[63:0] <7>
U48B U48A
<7> H_A#[16:3]
H_A#16 AA2 N2 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# <7> D[15]# D[47]#
H_A#15 Y3 A10 H_D#14 E23 AA26 H_D#46
D A[15]# PRDY# H_BPM#4 <6> D[14]# D[46]# D
H_A#14 AA3 B10 H_D#13 B23 Y23 H_D#45
A[14]# PREQ# H_BPM#5 <6> D[13]# D[45]#
H_A#13 U1 H_D#12 C26 V26 H_D#44
H_A#12 A[13]# H_D#11 D[12]# D[44]# H_D#43
Y1 A[12]# BNR# L1 H_BNR# <7> E24 D[11]# D[43]# U25
H_A#11 Y4 J3 H_D#10 D24 V24 H_D#42
A[11]# BPRI# H_BPRI# <7> D[10]# D[42]#
ADDRESS GROUP 0
H_A#10 H_D#9 H_D#41
DATA GROUP 0
2
W2 A[10]# B24 D[9]# D[41]# U26
H_A#9 T4 H_D#8 C20 AA23 H_D#40
DATA GROUP
H_A#8 A[9]# H_D#7 D[8]# D[40]# H_D#39
W1 A[8]# DBR# A7 H_DBRESET# <6,17> B20 D[7]# D[39]# R23
H_A#7 V2 H_D#6 A21 R26 H_D#38
H_A#6 A[7]# H_D#5 D[6]# D[38]# H_D#37
R3 A[6]# B26 D[5]# D[37]# R24
H_A#5 V3 H_D#4 A24 V23 H_D#36
H_A#4 A[5]# H_D#3 D[4]# D[36]# H_D#35
U4 A[4]# DEFER# L4 H_DEFER# <7> B21 D[3]# D[35]# U23
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# <7> D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
<7> H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# <7> D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 REQ[3]# <7> H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 <7>
H_REQ#2 T2 C23 W25
REQ[2]# <7> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <7>
H_REQ#1 P3 C22 W24
REQ[1]# <7> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <7>
H_REQ#0 R2 REQ[0]# H_D#31 H_D#63
<7> H_REQ#[4:0] N4 H_BR0# <7> K25 AF26
CONTROL
BR0# +VCCP H_D#30 D[31]# D[63]# H_D#62
N25 D[30]# D[62]# AF22
H_D#29 H26 AF25 H_D#61
H_IERR# H_D#28 D[29]# D[61]# H_D#60
IERR# A4 2 1 M25 D[28]# D[60]# AD21
OD R468 56Ohm H_D#27 N24 AE21 H_D#59
<7> H_A#[31:17] D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
A[31]# D[26]# D[58]#
3
H_A#30 H_D#25 H_D#57
DATA GROUP 1
AE1 A[30]# INIT# B5 H_INIT# <17> +VCCP J25 D[25]# D[57]# AD24
H_A#29 H_D#24 H_D#56
DATA GROUP
AF3 A[29]# M23 D[24]# D[56]# AF23
H_A#28 AD6 H_D#23 J23 AE22 H_D#55
A[28]# D[23]# D[55]#
ADDRESS GROUP 1
H_A#27 AE2 J2 H_D#22 G24 AD23 H_D#54
A[27]# LOCK# H_LOCK# <7> D[22]# D[54]#
2
H_A#26 AD5 H_D#21 F25 AC25 H_D#53
H_A#25 A[26]# R228 H_D#20 D[21]# D[53]# H_D#52
AC6 A[25]# H24 D[20]# D[52]# AC22
H_A#24 AB4 H_D#19 M26 AC20 H_D#51
H_A#23 A[24]# 54.9Ohm H_D#18 D[19]# D[51]# H_D#50
AD2 A[23]# L23 D[18]# D[50]# AB24
H_A#22 AE4 1% /* H_D#17 G25 AC23 H_D#49
1
H_A#21 A[22]# H_D#16 D[17]# D[49]# H_D#48
AD3 A[21]# RESET# B11 H_CPURST# <7> H23 D[16]# D[48]# AB25
H_A#20 AC3 L2 H_RS#2 J26 AD20
A[20]# RS[2]# <7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7>
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