Service Manuals, User Guides, Schematic Diagrams or docs for : benq BENQ_r55_Quanta_TW3A
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1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP TW3A- DESIGN DC/DC DC/DC DC/DC
CLOCKS
1
LAYER 2 : SGND1 +3VSUS +3VPCU +1.05V
+5VSUS +5VPCU +1.5V ICS954206
A LAYER 3 : IN1 A
LAYER 4 : IN2 RUN POWER AC/BATT PG43 PG38 PG37 PG 3
SW CONNECTOR
PG 40 Yonah/Merom
LAYER 5 : VCC CPU VR
31W/35W
LAYER 6 : IN3 PG 43 (478 Micro-FCPGA)
BATT
PG 40
LAYER 7 : SGND2 CHARGER PG 37
PG 4,5
LAYER 8 : BOT nVIDIA
PCI-Express 16X DC/DC
FSB NV72M/MV
VGA CORE
133MHZ (64 Bit B/W)
DDRII 667mhz LVDS(2 Channel) Panel Connector
DDRII-SODIMM1 Calistoga PM DDRII
DDRII VR PG 22 PG42
PG 16,17 945PM 16M*16(128MB)
TVOUT S-Video 32M*16(256MB)
B DDRII 667mhz Integraded VGA Function PG 35 (Bank*4)
DDRII-SODIMM2 B
PG 39 1466 BGA
PG 16,17 VGA VGA,DVI
PG 6,7,8,9,10,11 PG 23
DMI USB2.0 (P5) Bluetooth
USB2.0
interface PG 33
SATA - HDD (P0~P7)
SATA0
PG 29 USB2.0 (P0~P1,P4) USB2.0 I/O
Ports PG 26
ICH7-M PG 18~21
PATA - HDD
PATA 100 PCI-E, 1X LAN
PG 29 88E8038/88E8055 Magnetics RJ45
PG 25 PG 25
PG 24
652 BGA
Internal ODD PCI-E, 1X Mini PCI-E Card
CD-ROM PCI Express Mini Card
C PG 29 PCI-E, 1X PG 33 C
Azalia
PCI Bus 33MHz
Express Card x1
PG 12,13,14,15
NEW CARD Power Input RQ6
PG 33
Conexant Audio LPT PORT
CX20549-12 COM PORT Replicator
LPC TI PC7402 Daughter Board
PG 30 LAN
PG 27 VGA
Headphone
USB
IEEE1394 CONN 1394
AUDIO MDC DAA TPM1.2 KBC
PC87541V 3 in 1 Card reader USB X 2
Amplifier CX20548-A
PG28
PG 31 PG 32 PG 44 PG 36
X-Bus
PG 35
D D
Jack to Audio MODEM Key Touch Flash PCI ROUTING
Speaker Jacks RJ 11 Matrix Pad TABLE IDSEL INTERUPT DEVICE
PG 31 PG 30 PG 32 PG 34 PG 34 PG 36 REQ2# / GNT2# AD17 INTC#,INTD# TI 7402
PROJECT : TW3
Quanta Computer Inc.
Size Document Number Rev
B1A
Block Diagram
Date: Thursday, March 09, 2006 Sheet 1 of 47
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
2
Board Stack up Description
PCB Layers Voltage Rails
A A
Layer 1 TOP(Component,Other) Voltage Rails ON S0~S2 ON S3 ON S4 ON S5 Control signal
Layer 2 Ground Plane VCC_CORE Core voltage for Processor X VR_ON 0.726V~0.94V
VCCP Core voltage for CPU / NB X VR_ON
Layer 3 IN1
SMDDR_VTERM 0.9V for DDR2 Termination voltage X MAINON
Layer 4 IN2
RVCC1.5 X X X RVCC_ON
Layer 5 Power Plane
RVCC3 X X X RVCCD
Layer 6 IN3
Layer 7 Ground Plane
Layer 8 BOTTOM VCC1.5 X MAIND
VCC2.5 X MAINON
VCC3 X MAIND
Power On Sequencing Timing Diagram VCC5 X MAIND
VID 1.8VSUS X X SUSON
Tsft_star_vcc 3VSUS X X SUSD
VR_ON
Vboot Vid 5VSUS X X SUSD
Vcc-core Tboot
Tboot-vid-tr
CPU_UP Tcpu_up 3VPCU X X X X VL
5VPCU X X X X VL
B B
Vccp 9VPCU X X X X 5VPCU
Vccp_UP Tvccp_up
Vccgmch
GMCHPWRGD Tgmch_pwrgd
ACIN POWER ON TIMING
CLK_ENABLE# ACIN
IMVP4_PWRGD Tcpu_pwrgd Voltage Rails ON S0~S1 ON S3 ON S4 ON S5 Control signal
5VPCU/3VPCU
VCC_CORE Core voltage for Processor X VRON
NBSWON#
GMCH_VTT Core voltage for GMCH 1.05V X MAINON
SMDDR_VTERM 0.9V for DDR II Termination voltage X MAINON
Dothan Power-up Timing PWRBTN# To ICH7 SMDDR_VREF 0.9V for DDR II Reference Voltage X MAINON
Specifications
From 87541 GMCH_1.5V X MAINON
Td
S5_ON 1.8VSUS 1.8V for DDR II voltage X X SUSON
RESET# To ICH7
+2.5V X MAINON
RSMRST#
From ICH7
3VPCU X X X X VL
SUSB#,SUSC# 3VSUS X X SUSON
+3V X MAINON
BCLK From 87541
SUSON 5VPCU X X X X VL
Tc From 87541 5VSUS X X SUSON
+5V X MAINON
MAINON
Te From 87541
PWRGOOD VSUS,VCC
From 87541
C C
VR_ON
Tf
Ta Tb VIN POWER SOURCE X X X X
VCCP/1.05V
VCC VCORE_CPU PCI DEVICE IDSEL# REQ# / GNT# Interrupts
Vcc,boot
VID[5:0] PCI7402 AD17 REQ2# / GNT2# PIRQ C/D
CLK_EN# To clock generator
99ms < t 214
PWROK To GMCH/other PCI device
PLTRST#\PCIRST#
VCCP
From ICH7 to CPU
H_PWRGD
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild 2ms Form GMCH to CPU
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time H_CPURST#
Te=Vcc,boot vaild to PWRGOOD assertion time
D D
PROJECT : TW3
Quanta Computer Inc.
Size Document Number Rev
B1A
System Information
Date: Thursday, March 09, 2006 Sheet 2 of 47
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
FSC FSB FSA
1
0
0
0
1
1
CPU
100
133
SRC
100
100
PCI
33
33
Place these termination to close
CK410M. Cause those Pin-out is
for Current-Mode.
3
0 1 1 166 100 33
0 1 0 200 100 33 R135 1 2 49.9/F
R131 1 2 49.9/F
A 0 0 0 266 100 33 C419 33p/50V VDDA_CR R133 1 A
2 49.9/F
1 0 0 333 100 33 2 1 XIN R134 1 2 49.9/F
1
1 1 0 400 100 33 <500mil
Y1 U13
37
38
1 1 1 RSVD 100 33 R145 33/F
C434 14.318MHZ 50 52 14M_REF 1 2
VDDA
VSSA
14M_ICH 14
2
33p/50V XTAL_IN REF RP33
1
2 1 XOUT 49 44 R_HCLK_CPU 4 3
XTAL_OUT CPU0 CLK_CPU_BCLK 4
43 R_HCLK_CPU# 2 1 33x2 C405
CPU0# CLK_CPU_BCLK# 4
RP34 *10p
2
CLK_EN# 10 41 R_HCLK_MCH 4 3
14,37 CLK_EN# VTT_PWRGD#/PD# CPU1 CLK_MCH_BCLK 6
14 PM_STPPCI# PM_STPPCI# 55 40 R_HCLK_MCH# 2 1 33x2
PCI_STOP# CPU1# CLK_MCH_BCLK# 6
14 PM_STPCPU# PM_STPCPU# 54 RP35
TI_CLK48M R181 1 CPU_STOP#
28 TI_CLK48M 2 10 CPU2_ITP/SRC7 36 R_PCIE_VGA 4 3 CLK_PCIE_VGA
CLK_PCIE_VGA 18
CLKUSB_48 R180 1 2 10 35 R_PCIE_VGA# 2 1 CLK_PCIE_VGA#
14 CLKUSB_48 CPU2#_ITP/SRC7# CLK_PCIE_VGA# 18
RP31 33x2
CGCLK_SMB 46 CK-410M 33 R_PCIE_LAN 4 3 CLK_PCIE_LAN
SCLK SRC6 CLK_PCIE_LAN 24
SMbus address D2 CGDAT_SMB 47 32 R_PCIE_LAN# 2 1 CLK_PCIE_LAN#
SDATA SRC6# CLK_PCIE_LAN# 24
33x2
R426 1 2 8.2K/F FSA 12 31 R_MCH_3GPLL RP32
4 3 CLK_MCH_3GPLL
4,7 CPU_MCH_BSEL0 FSA/USB_48 SRC5 CLK_PCIE_3GPLL 7
16 30 R_MCH_3GPLL# 2 1 CLK_MCH_3GPLL#
+3VRUN 4,7 CPU_MCH_BSEL1 FSB/TEST_MODE SRC5# CLK_PCIE_3GPLL# 7
R408 1 2 8.2K/F FSC 53 33x2
4,7 CPU_MCH_BSEL2 FSC/TEST_SEL
26 R_PCIE_SATA RP40
2 1 CLK_PCIE_SATA
SRC4 CLK_PCIE_SATA 12
VDDREF_CR 48 27 R_PCIE_SATA# 4 3 CLK_PCIE_SATA#
VDD_REF SRC4# CLK_PCIE_SATA# 12
CLKVDD 42 33x2
VDD_CPU
2
24 R_PCIE_ICH RP39
2 1 CLK_PCIE_ICH
SRC3 CLK_PCIE_ICH 13
R172 CLKVDD1 1 25 R_PCIE_ICH# 4 3 CLK_PCIE_ICH#
VDD_PCI_1 SRC3# CLK_PCIE_ICH# 13
10K 7 33x2
VDD_PCI_2 R_PCIE_MINI RP38 CLK_PCIE_MINI
B
SRC2 22 2 1 CLK_PCIE_MINI 33 B
CLKVDD 21 23 R_PCIE_MINI# 4 3 CLK_PCIE_MINI#
CLK_PCIE_MINI# 33
1
FSA VDD_SRC0 SRC2# 33x2
28 VDD_SRC1
34 19 R_PCIE_NEW RP37
2 1 CLK_PCIE_NEW_C
VDD_SRC2 SRC1 CLK_PCIE_NEW_C 33
2
20 R_PCIE_NEW# 4 3 CLK_PCIE_NEW_C#
SRC1# CLK_PCIE_NEW_C# 33
R171 VDD48_CR 11 33x2
VDD_48
*10K_NC SRC0 17
1 2 IREF 39 18
R132 475/F IREF SRC0#
0816a
1
5 R_PCLK_SIO R169 1 2 33/F
PCI5 PCLK_541 36
Iref=5mA, 4 R_PCLK_PCM R176 1 2 33/F
PCI4 PCLK_PCM 27
3 R_PCLK_LPC_DEBUG R173 1 2 33/F
GND_PCI_1
GND_PCI_2
Ioh=4*Iref PCI3 PCLK_LPC_DEBUG 33
GND_SRC
GND_CPU
GND_REF
14 56 R_PCLK_TPM R144 1 2 *33_4
DOT96 PCI2 PCLK_TPM 44
GND_48
15 9 R_PCLK_ICH R179 1 2 33/F
DOT96# PCIF1 PCLK_ICH 13
8 PCIF0 1 2
PCIF0/ITP_EN R177 10K
PCIF1
1:100 Mhz
13
51
2
6
29
45
ICS954206AGLFT 0:96 Mhz
CT_0505: Change footprint to 250mA ( MAX. )
1
R170
2
*10K
+3VRUN
120 ohms@100Mhz
L21 TSSOP56-8_1-5 from 1 2
+3VRUN 1 2 0.047u/10V 0.047u/10V CLKVDD TSSOP56-240 R178 10K
HB-1T2012-121JT
1
1
1
1
1
C438 C408 C445 C406 C432
Tie to VCC (Logic 1) is for ITP using. CLK_PCIE_VGA 1 2
CLK_PCIE_VGA# RP28 3 4 49.9x2
Bypass CAPs need to
2
2
2
2
2
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