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, ... V,. CRAY-1S
RESEARCH. INC. COMPUTER SYSTEM
liD SUBSYSTEM SOFTWARE
FOR TRAINING PURPOSES ONLY
I/O SUBSYSTEM SOFTWARE
COPYRIGHT 1981 BY CRAY RESEARCH, INC. THIS MANUAL OR PARTS
THEREOF MAY NOT BE REPRODUCED IN ANY FORM WITHOUT PERMISSION OF
CRAY RESEARCH, INC.
RECORD OF REVISION RESEARCH~lNC~ PUBLICATION NUMBER
Each time this manual is revised and reprinted, all chan~es issued against the previous version in the form of change packets are
incorporated into the new version and the new version IS assigned an alphabetic level. Between reprints, changes may be issued
against the current version in the form of change packets. Each change packet is assigned a numeric designator, starting with
01 for the first change packet of each revision level.
Every page changed by a reprint or by a change packet has the revision level and change packet number in the lower righthand
corner. Changes to part of a page are noted by a change bar along the margin of the page. A change bar in the margin opposite
the page number indicates that the entire page is new; a dot in the same place indicates that information has been moved from
one page to another, but has not otherwise changed.
Requests for copies of Cray Research, Inc. publications and comments about these publications should be directed to:
CRAY RESEARCH, INC.,
1440 Northland Drive,
Mendota Heights, Minnesota 55120
September, 1980 - Original printing
A November, 1980 - Reprint with revision. Changes include
addition of detail on concentrator software.
B January 1981 - Reprint with revision. Changes to add more
detailed flow diagrams.
C March 1981 - Reprint with reV1Slon. Changes include addition
of interactive station software and deadstart procedures.
D September 1981 - Reprint with revision. Changes to add more
detail on Disk I/O and IDS Chassis Layouts.
TABLE OF CONTENTS
PART 1 - I/O SUBSYSTEM HARDWARE
I. SYSTEf1 OVERVI E\\}
I/O SUBSYSTEM 1.1
INDIVIDUAL I/O PROCESSOR 1.6
MODEL NUMBERING CONVENTION 1.7
AVAILABLE CONFIGURATIONS AND PROCESSOR
2. I/O PROCESSOR LOCAL MEMORY
ADDRESSING SCHEME 2.4
3. COMPUTATION SECTION
BASIC COMPONENTS 3.1
INSTRUCTION CONTROL NETWORK 3.4
OP~RAND REGISTERS 3.12
FUNCTIONAL UNITS 3.13
ADDEND REGISTER 3.15
4. I/O SECTION
ACCUMULATOR CHANNELS 4.4
DI1A CHANNELS 4.4
OVER VI E\41 OF I/O 4.5
DEDICATED CHANNELS 4.6
INTERFACE CHANNELS 4.16
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