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                                                                                                                                      June 1997

 NDP6030PL / NDB6030PL
 P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description                                                             Features

 These P-Channel logic level enhancement mode power field                           -30 A, -30 V. RDS(ON) = 0.042  @ VGS= -4.5 V
 effect transistors are produced using Fairchild's proprietary,                                   RDS(ON) = 0.025  @ VGS= -10 V.
 high cell density, DMOS technology. This very high density                         Critical DC electrical parameters specified at elevated
 process is especially tailored to minimize on-state resistance.                    temperature.
 These devices are particularly suited for low voltage
 applications such as DC/DC converters and high efficiency                          Rugged internal source-drain diode can eliminate the need
 switching circuits where fast switching, low in-line power loss,                   for an external Zener diode transient suppressor.
 and resistance to transients are needed.
                                                                                    High density cell design for extremely low RDS(ON).

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