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                                                                                                                                         July 1996

     N-Channel Logic Level Enhancement Mode Field Effect Transistor

     General Description                                                          Features

     These N -Channel logic level enhancement mode power field                          1.7 A, 20 V. RDS(ON) = 0.14  @ VGS= 2.7 V
     effect transistors are produced using Fairchild's proprietary,                                  RDS(ON) = 0.11  @ VGS= 4.5 V.
     high cell density, DMOS technology. This very high density
     process is especially tailored to minimize on-state resistance.                    Industry standard outline SOT-23 surface mount package
     These devices are particularly suited for low voltage                              using poprietary SuperSOTTM-3 design for superior thermal
     applications in notebook computers, portable phones, PCMCIA                        and electrical capabilities.
     cards, and other battery powered circuits where fast switching,
     and low in-line power loss are needed in a very small outline                      High density cell design for extremely low RDS(ON).
     surface mount package.
                                                                                        Exceptional on-resistance and maximum DC current



                                                                                                           G                  S

Absolute Maximum Ratings                            T A = 25

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