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                                                                                                                                    June 1997

 P-Channel Logic Level Enhancement Mode Field Effect Transistor

 General Description                                                              Features

 SuperSOTTM-3 P-Channel logic level enhancement mode power                            -1.2 A, -20 V, RDS(ON) = 0.27  @ VGS= -2.7 V
 field effect transistors are produced using Fairchild's                                             RDS(ON) = 0.2  @ VGS = -4.5 V.
 proprietary, high cell density, DMOS technology. This very high
 density process is especially tailored to minimize on-state                          Very low level gate drive requirements allowing direct
 resistance. These devices are particularly suited for low voltage                    operation in 3V circuits. VGS(th) < 1.0V.
 applications such as notebook computer power management,
                                                                                      Proprietary package design using copper lead frame for
 portable electronics, and other battery powered circuits where
                                                                                      superior thermal and electrical capabilities.
 fast high-side switching, and low in-line power loss are needed
 in a very small outline surface mount package.                                       High density cell design for extremely low RDS(ON).

                                                                                      Exceptional on-resistance and maximum DC current
                                                                                      Compact industry standard SOT-23 surface         Mount



                                                                                                   G                   S

Absolute Maximum Ratings                      T A = 25

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