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2N5564/5565/5566
Vishay Siliconix
Matched N-Channel JFET Pairs
PRODUCT SUMMARY
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Typ (pA) jVGS1 - VGS2j Max (mV)
2N5564 -0.5 to -3 -40 7.5 -3 5
2N5565 -0.5 to -3 -40 7.5 -3 10
2N5566 -0.5 to -3 -40 7.5 -3 20
FEATURES BENEFITS APPLICATIONS
D Two-Chip Design D Tight Differential Match vs. Current D Wideband Differential Amps
D High Slew Rate D Improved Op Amp Speed, Settling Time D High-Speed,
D Low Offset/Drift Voltage Accuracy Temp-Compensated,
D Low Gate Leakage: 3 pA D Minimum Input Error/Trimming Requirement Single-Ended Input Amps
D Low Noise: 12 nV/Hz @ 10 Hz D Insignificant Signal Loss/Error Voltage D High-Speed Comparators
D Good CMRR: 76 dB D High System Sensitivity D Impedance Converters
D Minimum Parasitics D Minimum Error with Large Input Signals D Matched Switches
D Maximum High Frequency Performance
DESCRIPTION
The 2N5564/5565/5566 are matched pairs of JFETs mounted The hermetically-sealed TO-71 package is available with full
in a TO-71 package. This two-chip design reduces parasitics military processing (see Military Information).
for good performance at high frequency while ensuring
extremely tight matching. This series features high
breakdown voltage (V(BR)DSS typically > 55 V), high gain For similar products see the low-noise U/SST401 series, and
(typically > 9 mS), and <5 mV offset between the two die. the low-leakage 2N5196/5197/5198/5199 data sheets.
TO-71
S1 G2
1 6
D1 2 5 D2
3 4
G1 S2
Top View
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C
Gate-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "80 V Power Dissipation : Per Sidea . . . . . . . . . . . . . . . . . . . . . . . . 325 mW
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Totalb . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
Notes
Lead Temperature (1/16" from case for 10 sec.) . . . . . . . . . . . . . . . . . . 300 _C a. Derate 2.6 mW/_C above 25_C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 200_C b. Derate 5.2 mW/_C above 25_C
Document Number: 70254 www.vishay.com
S-50150--Rev. E, 24-Jan-05 1
2N5564/5565/5566
Vishay Siliconix
SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)
Limits
2N5564 2N5565 2N5566
Parameter Symbol Test Conditions Typa Min Max Min Max Min Max Unit
Static
Gate-Source
V(BR)GSS IG = -1 mA, VDS = 0 V -55 -40 -40 -40
Breakdown Voltage
V
Gate-Source
VGS(off) VDS = 15 V, ID = 1 nA -2 -0.5 -3 -0.5 -3 -0.5 -3
Cutoff Voltage
Saturation Drain
IDSS VDS = 15 V, VGS = 0 V 20 5 30 5 30 5 30 mA
Currentb
VGS = -20 V, VDS = 0 V -5 -100 -100 -100 pA
Gate Reverse Current IGSS
TA = 150_C -10 -200 -200 -200 nA
VDG = 15 V, ID = 2 mA -3 pA
Gate Operating Currentc IG
TA = 125_C -1 nA
Drain-Source
rDS(on) VGS = 0 V, ID = 1 mA 50 100 100 100 W
On-Resistance
Gate-Source Voltagec VGS VDG = 15 V, ID = 2 mA -1.2
Gate-Source V
VGS(F) IG = 2 mA , VDS = 0 V 0.7 1 1 1
Forward Voltage
Dynamic
Common-Source
gfs 9 7.5 12.5 7.5 12.5 7.5 12.5 mS
Forward Transconductance VDS = 15 V, ID = 2 mA
Common-Source f = 1 kHz
gos 35 45 45 45 mS
Output Conductance
Common-Source VDS = 15 V, ID = 2 mA
gfs 8.5 7 7 7 mS
Forward Transconductanced f = 100 MHz
Common-Source
Ciss 10 12 12 12
Input Capacitance
VDS = 15 V ID = 2 mA
V,
Common-Source pF
f = 1 MHz
Reverse Transfer Crss 2.5 3 3 3
Capacitance
Equivalent Input VDS = 15 V, ID = 2 mA nV/
en 12 50 50 50
Noise Voltage f = 10 Hz Hz
Noise Figure NF RG = 10 MW 1 1 1 dB
Matching
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