Service Manuals, User Guides, Schematic Diagrams or docs for : . Electronic Components Datasheets Various datasheets 74ls76
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>> Download 74ls76 documenatation <<Text preview - extract from the document SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level DUAL JK FLIP-FLOP
of the J and K inputs will perform according to the Truth Table as long as mini- WITH SET AND CLEAR
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions. LOW POWER SCHOTTKY
J SUFFIX
MODE SELECT -- TRUTH TABLE CERAMIC
CASE 620-09
INPUTS OUTPUTS 16
OPERATING MODE 1
SD CD J K Q Q
Set L H X X H L
Reset (Clear) H L X X L H
*Undetermined L L X X H H
N SUFFIX
Toggle H H h h q q
PLASTIC
Load "0" (Reset) H H l h L H
16 CASE 648-08
Load "1" (Set) H H h l H L
Hold H H l l q q 1
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level D SUFFIX
L,l = LOW Voltage Level
SOIC
X = Immaterial 16
1 CASE 751B-03
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
LOGIC DIAGRAM
LOGIC SYMBOL
Q 2 7
Q
SD 15 SD 11
16 K Q 12 K Q
1 CP 6 CP
CLEAR (CD) SET (SD)
K 4 J C Q 14 9 J C Q 10
J D D
3 8
CLOCK (CP) VCC = PIN 5
GND = PIN 13
FAST AND LS TTL DATA
5-1
SN54/74LS76A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54
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