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THE AES - 80
MICROPROCESSOR
REFERENCE
MANUAL
~(JTOMATIC ELECTRONIC SYSTEMS INC., 5455 PARE sr, MONTREAL 309 CANADA, TEL. (514) 735- 6581
~ES DATA INC., P.O. BOX 143 ST ALBANS, VERMONT 05478, TEL. (802) 524-3660
: I : :
MICROPROCESSOR
REFERENCE MANUAL
PROPRIETARY NOTICE: This publication contains proprietary
information of Automatic Electronic Systems Inc. and shall
not be reproduced, copied, or used for any purpose other
than the consideration of technical content without the
express written permission of a duly authorized represen-
tative of Automatic Electronic Systems Inc.
AUTOMATIC ELECTRONIC SYSTEMS INC.,
5455 Pare Street
Montreal 309
TEL. : ( 514 ) 7 3 5 - 6 5 8 1
AES MICROPROCESSOR
TABLE OF CONTENTS
Page
I . System Design Features 1
1.~ General Characteristics 1
1.1 Physical Configuration 1
1.2 System Organization 2
1.3 Instruction Memory 2
1.4 Data Memory 3
1.5 Arithmetic Logic Unit 4
1.6 Registers 4
1.6.~ P-Register 4
1.6.1 A-Register 4
1.6.2 L-Register 4
1.6.3 LA-Register 5
1.6.4 B-Register 5
1.6.5 U-Register 5
1.7 Decision Flags 5
1.8 Push Do\vn Stack 6
1.9 Instruction Timing 6
1.1~ Input/Output Interface 6
II. Microinstruction Repertoire 1~
2.~ Instruction Formats 1~
2.~.~ Function 1~
2.~.1 Decision l~
2.~.2 ROM Address 11
2.~.3 RAM Address 11
2.~.4 Data Literal 11
2.~.5 ALU Literal 12
2.1 Terms, Mnemonics and Symbols 12
2.2 Load Data Bus Instructions 13
2.3 Load Literal Buffer Instruction 14
2.4 ALU Mode Instruction 14
2.5 Load Accumulator Instructions 17 .
2.6 RAM Address Instructions 17
2.7 Store Into RAM Instruction 18
2.8 Conditional Branch Instructions 18
2.9 Set Page Instruction 19
2.1~ Unconditional Jump Instruction 19
2.11 Jump to Subroutine Instruction 2~
2.12 Return from Subroutine Instruction 2~
2.13 NOP and HALT Instructions 2~
2.14 PORC and the RST Instruction 21
2.15 Real TIME CLOCK and the RTC Instruction 21
Page
III. Input/Output 23
3 .~ serial I/O 23
3.~.1 I/O Bus Structure 23
3.~.2 Modular System Unit Bus Interface 24
3.~.3 Typical I/O Board 24
3.~.4 Serial I/O Interrupt 25
3.1 Interrupt Structure 26
3.2 Parallel I/O 26
3.3 Multiprocessor Configuration 27
3.4 I/O Instructions 27
3~4.l U-Register Instructions 28
3.4.2 I/O Register Select Instructions 28
3.4.3 I/O Channel Select Instruction 28
3.4.4 Serial I/O Clock, Load and R/W 29
Instructions
3.4.5 Relinquish Bus Control Instructions 29
3.4.6 Serial I/O Timing Instructions 29
3.4 . 7 Interrupt Instructions 3~
3.4.8 Other I/O Instructions 31
IV. Timing 35
4. JJ Function and Literal Timing 35
4.1 Branch Instruction Timing 35
4.2 Subroutine Timing 35
4.3 I/O Timing 35
V. Program Development and Control Console 41
VI. Software Development 45
VII. Appendices
A.I Table of Binary to Octal to ASCII Conversion A.l
A.2 Operation Code List B.l
Illustrations
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