Service Manuals, User Guides, Schematic Diagrams or docs for : . Various Div Laptop Schema`s BenQ Joybook A51E
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1 2 3 4 5 6 7 8
01
CPU CORE MAX8771
POWER VCORE
SYSTEM MAX8734AEEI+
PG 32
BQ2L BLOCK DIAGRAM
POWER(3/5V) PG 33
CPU THERMAL
SYSTEM POWER MAX8743 SENSOR
A
(VCCP) PG 36 CPU Yonah/Merom GMT781
PG 31 A
SYSTEM POWER APL5331 479 Pins (uPGA)
(+1.5V) PG 37
14.318MHz
CPUCLK,CPUCLK#
SYSTEM POWER MAX8632ETI+
PG 4,5
(1.8VSUS/0.9V SMDDR_VREF)
PG 34 CLOCK GEN MEM CLK BUF
FSB SBLINKCLK, SBLINKCLK#
ICS9LPR600
BATT CHARGER 533M/667M NBSRCCLK, NBSRCCLK# 56pins ICS9P935
MAX8724 PG 35
PG 3 PG 3
BATTERY CONNECTOE HTREFCLK USB6
PG35
OSC14M
New Card
CRT port R.G,B SiS M662MX
PG 21
PG 18 DDRII-SODIMM1
DDRII 533,667 MHz
B Integraded VGA Function USB4 B
PG 16,17
LCD Panel LVDS X1 801 BGA (31X31)
PG 23 DDRII 533,667 MHz Mini PCIE /
SiS 307LV HDV I/F DDRII-SODIMM2
PG 6,7,8,9 WLAN
S-VIDEO TV-OUT PG 16,17 PG 24
PG 18 DMI X4 NBSRCCLK, NBSRCCLK#
PG 10 32.768KHz
PCI-Express
MII I/F PHY 10/100 Magnetics RJ45PG 25
RTL8201CL PG 25
SATA 150MB PG 22
SATA - HDD PG 26
SiS 966L 33MHZ, 3.3V PCI
ATA 66/100/133
IDE - ODD PG 26 Azalia
588 BGA (27X27)
24.576MHz
C USB 2.0 C
USB PORT 1 PG 30
PG 12,13,14,15 PWRCLKN DIB_DATAN IEEE 1394
PWRCLKP DIB_DATAP
PG 20
USB PORT 3 PG 30
CARDBUS R5C832
PG 19,20
4 IN 1
USB PORT 5 PG 21
PG 30
MDC Azalia
32.768KHz AUDIO CODEC
USB PORT 7 PG 30 PG 29 ALC262H PG27
LPC
Bluetooth PG 29 USB PORT 0 PG 29 PC87541
AMP
TQFP 176pins MAX9755
CIR PG 29
USB PORT 2 PG 29 PG 31
PG28
D
WIRE D
Touch Key FLASH QUANTA
FAN RJ11 LINE IN MIC INT SPK HP
PAD Board ROM
PG24 PG29 PG30 PG31 PG25 PG28 PG 27 PG28 PG28 Title
COMPUTER
BLOCK DIAGRAM
Size Document Number Rev
Custom BQ2L MAIN BOARD 1A
Date: Friday, August 25, 2006 Sheet 1 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
02
Board Stack up Description
PCB Layers Voltage Rails
A A
Layer 1 TOP(Component,Other) Voltage Rails ON S0~S2 ON S3 ON S4 ON S5 Control signal
Layer 2 Ground Plane VCC_CORE Core voltage for Processor X VR_ON 0.726V~0.94V
VCCP Core voltage for CPU / NB X VR_ON
Layer 3 IN1
SMDDR_VTERM 0.9V for DDR2 Termination voltage X MAINON
Layer 4 IN2
RVCC1.5 X X X RVCC_ON
Layer 5 Power Plane
RVCC3 X X X RVCCD
Layer 6 IN3
Layer 7 Ground Plane
Layer 8 BOTTOM VCC1.5 X MAIND
VCC2.5 X MAINON
VCC3 X MAIND
Power On Sequencing Timing Diagram VCC5 X MAIND
VID 1.8VSUS X X SUSON
Tsft_star_vcc 3VSUS X X SUSD
VR_ON
Vboot Vid 5VSUS X X SUSD
Vcc-core Tboot
Tboot-vid-tr
CPU_UP Tcpu_up 3VPCU X X X X VL
5VPCU X X X X VL
B B
Vccp 9VPCU X X X X 5VPCU
Vccp_UP Tvccp_up
Vccgmch
GMCHPWRGD Tgmch_pwrgd
ACIN POWER ON TIMING
CLK_ENABLE# ACIN
IMVP4_PWRGD Tcpu_pwrgd Voltage Rails ON S0~S1 ON S3 ON S4 ON S5 Control signal
5VPCU/3VPCU
VCC_CORE Core voltage for Processor X VRON
NBSWON#
GMCH_VTT Core voltage for GMCH 1.05V X MAINON
SMDDR_VTERM 0.9V for DDR II Termination voltage X MAINON
Dothan Power-up Timing PWRBTN# To ICH7 SMDDR_VREF 0.9V for DDR II Reference Voltage X MAINON
Specifications
From 87541 GMCH_1.5V X MAINON
Td
S5_ON 1.8VSUS 1.8V for DDR II voltage X X SUSON
RESET# To ICH7
+2.5V X MAINON
RSMRST#
From ICH7
3VPCU X X X X VL
SUSB#,SUSC# 3VSUS X X SUSON
+3V X MAINON
BCLK From 87541
SUSON 5VPCU X X X X VL
Tc From 87541 5VSUS X X SUSON
+5V X MAINON
MAINON
Te From 87541
PWRGOOD VSUS,VCC
From 87541
C C
VR_ON
Tf
Ta Tb VIN POWER SOURCE X X X X
VCCP/1.05V
VCC VCORE_CPU PCI DEVICE IDSEL# REQ# / GNT# Interrupts
Vcc,boot
VID[5:0] PCI7402 AD20 REQ2# / GNT2# PIRQ C/D
CLK_EN# To clock generator
99ms < t 214
PWROK To GMCH/other PCI device
PLTRST#\PCIRST#
VCCP
From ICH7 to CPU
H_PWRGD
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild 2ms Form GMCH to CPU
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time H_CPURST#
Te=Vcc,boot vaild to PWRGOOD assertion time
D D
QUANTA
Title
COMPUTER
FRONTPAGE
Size Document Number Rev
Custom BQ2L MAIN BOARD 1A
Date: Friday, August 25, 2006 Sheet 2 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3VRUN
120 ohms@100Mhz
1
L65
2
HB-1T2012-121JT
CLK_VDD 2
14
U11
VDDREF
VDDPCI
CPUT_L0
CPUC_L0
55
54
R_HCLK_CPU
R_HCLK_CPU#
R_HCLK_CPU
R_HCLK_CPU#
R_HCLK_MCH
R_HCLK_MCH#
RP33
4
2
4
2
33x2
3
1
3 RP34
1
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
03
1
1
1
1
1
1
1
1
C608 C618 C617 C612 C619 C613 C615 C609 C616 19 52 R_HCLK_MCH 33x2
VDDPCI CPUT_L1 R_HCLK_MCH# R_CLK_PCIE_DN0 2
23 VDDZ CPUC_L1 51 1 CLK_PCIE_DN0 6
22u/6.3V_8 24 R_CLK_PCIE_DP0 4 3 CLK_PCIE_DP0 6
2
2
2
2
2
2
2
2
VDD48 R_CLK_PCIE_DP0 RP37 33x2
56 VDDCPU PCIET_L0 44
39 43 R_CLK_PCIE_DN0 R_PCIE_ICH# 2 1
VDDPCIEX PCIEC_L0 CLK_PCIE_ICH# 13
0.1u/10V 0.1u/10V 0.1u/10V 0.1u/10V 0.1u/10V 0.1u/10V 0.1u/10V 29 41 R_PCIE_ICH R_PCIE_ICH 4 3
VDDPCIEX PCIET_L1 CLK_PCIE_ICH 13
0.1u/10V 40 R_PCIE_ICH# RP38 33x2
+1.05V +3VRUN +3VRUN PCIEC_L1 R_PCIE_MINI R_PCIE_MINI#
A
7 GNDREF PCIET_L2 38 2 1 CLK_PCIE_MINI# 24 A
8 37 R_PCIE_MINI# R_PCIE_MINI 4 3
GNDPCI PCIEC_L2 CLK_PCIE_MINI 24
13 36 R_PCIE_NEW RP39 33x2
GNDPCI PCIET_L3 R_PCIE_NEW# R_PCIE_NEW#
20 GNDZ PCIEC_L3 35 2 1 CLK_PCIE_NEW_C# 21
27 34 R_PCIECLK307 R_PCIE_NEW 4 3
GND48 PCIET_L4F CLK_PCIE_NEW_C 21
2
2
2
53 33 R_PCIECLK307# RP40 33x2
R274 R263 R267 GNDCPU PCIEC_L4F R_PCIET_L5 R_PCIECLK307#
42 GNDPCIEX PCIET_L5F 31 2 1 CLK_PCIE_307# 10
*10K *10K *10K 32 30 R_PCIET_L5# R_PCIECLK307 4 3
GNDPCIEX PCIEC_L5F CLK_PCIE_307 10
RP41 33x2
49 R_PCIE_SATA R_PCIE_SATA# 2 1 CLK_PCIE_SATA# 14
1
1
1
CLKGEN_VTTPWRGD R273 *0 CLKGEN SATACLKT_L R_PCIE_SATA# R_PCIE_SATA
1 VTTPWRGD/PD#/(CLK_STOP#) SATACLKC_L 48 4 3 CLK_PCIE_SATA 14
RP35 33x2
3
VR_PWRGD_CK R272 0 21 ZCLK0 R289 22 ZCLK0_NB
ZCLK0 ZCLK0_NB 7
2 Q24 22 ZCLK1 R290 22 ZCLK1_SB
ZCLK1 ZCLK1_SB 12
13 PM_STPCPU# PM_STPCPU# R276 0 STPCPU#_C 28
*(CPU_STOP#)/RESET#
3
3 CLKGEN_FSL0 2 1 REFCLK0_NB
REFCLK0_NB 7
1
Q23 *MMBT3904 *FSL0/REF0_2x CLKGEN_FSL1 REFCLK1_SB
2 **FSL1/REF1_2x 4 4 3 REFCLK1_SB 13
L64 RP43 33x2
*MMBT3904 CLK_VDDA CLKGEN_FSL2 R282 1
+3VRUN 2 1 50 9 2 33 SB_PCI_CLK0 SB_PCI_CLK0 12
1
HB-1T2012-121JT VDDA **FSL2/PCICLK0_2x CLKGEN_FS3
**FS3/PCICLK1_2x 10
120 ohms@100Mhz 11 CLKGEN_FS4 R283 1 2 33 PCLK_LPC_DEBUG
**FS4/PCICLK2 PCLK_LPC_DEBUG 24
1
1
12 CLKGEN_STOP# R284 1 2 *33
C614 C611 C610 *(PCI_STOP#)/PCICLK3 CLKGEN_MODE R285 1 PCLK_R5C832
**MODE/PCICLK4 15 2 33 PCLK_R5C832 19
10u/10V_8 0.1u/10V 0.01u/16V 47 16 CLKGEN_EQ0 R488 0 PCIE_CLKREQ# 24
2
2
GNDA (PECLKREQ0#)/PCICLK5 CLKGEN_EQ1 R287 0
(PECLKREQ1#)/PCICLK6 17 NEW_CLKREQ# 21
18 CLKGEN_CLK7 R288 1 2 33 PCLK_541
PCICLK7 PCLK_541 31
CGDAT_SMB 45 26 SEL24M_48M
CGCLK_SMB SDATA **SEL24_48#/24_48MHz
46 SCLK
25 USB_12M R291 0 USB_12M_SB
12MHz USB_12M_SB 14
B B
+3VRUN
X1
X2
C Rev: Change Y1 to BG614318081(TXC)
2nd: BG614318K02(FCE) ICS9LPR600_TSSOP-56P
5
6
2
4
<500mil CLK_PCIE_MINI# 3 4 *49.9x2
Y3
CLKGEN_MODE: 1->Mobil; 0->Desktop. CLK_PCIE_MINI 1 2 RP29
RP36 1 2
2.2Kx2 SEL24_48M#: 1->24MHZ; 0->48MHZ R_PCIET_L5# 2 1 PCIET_L5# CLK_PCIE_NEW_C# 3 4 *49.9x2
2
Q43 XIN R_PCIET_L5 4 3 PCIET_L5 CLK_PCIE_NEW_C 1 2 RP30
14.318MHZ XOUT RP42 *33x2
PCICLK5: 1->Notebook; 0->Desktop
1
3
1
3 1 CGDAT_SMB C391 CLK_PCIE_SATA# 3 4 *49.9x2
21 PDAT_SMB CGDAT_SMB 13,16,24
1
C392 PCICLK6: 1->Notebook; 0->Desktop CLK_PCIE_SATA 1 2 RP26
27p/50V
2
RHU002N06 27p/50V ICS9LPR600 CLK_PCIE_ICH# 3 4 *49.9x2
2
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