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5 4 3 2 1
Pamirs-Discrete Block Diagram SYSTEM DC/DC
TPS51120
INPUTS OUTPUTS
Project code : 91.4S401.001 5V_S3
Intel CPU DCBATOUT
PCB P/N :06230 3V_S5
D
CLK GEN Meron 2M/4M SV SYSTEM DC/DC D
FSB:667 or 800 MHz
Revision : SC MAX8743
ICS9LPRS355A 4,5,6
3 INPUTS OUTPUTS
RGB CRT CRT 13 1D05V_S0
Host BUS DCBATOUT
1D8V_S3
533/667MHz
LVDS LCD 14 SYSTEM DC/DC
DDRII DDRII 667 Channel A
FAN5234
Slot 0 Crestline-GM/GML nVIDIA
533/667 13 INPUTS OUTPUTS
AGTL+ CPU I/F DDR I/F SVIDEO TVOUT 13 VGA_CORE_S0
DCBATOUT
DDRII INTEGRATED GRAHPICS NB8M-GS 11A
Slot 1 DDR II 667 Channel B PCIE x 16 38,39,40
533/667 14
LVDS, CRT I/F 7,8,9,10,11,12
MAXIM CHARGER
MAX8725
C
INPUTS OUTPUTS C
1394 1394 DMI I/F
25 BT+
Ricoh 100MHz
CAMERA32 DCBATOUT 18V 3.0A
R5C833 PCI
5V 100mA
SD/SDIO/MMC
CardReader
MS/MS Pro/xD
25 24,25 INTEL BLUE
TOOTH 32 CPU DC/DC
MAX8736ETL
ICH8-M USB 2.0 USB x 3 23
INPUTS OUTPUTS
10/100 NIC LCI 10 USB 2.0/1.1 ports
RJ45 Marvell 88E8039 27 VCC_CORE
ETHERNET (10/100/1000Mb)
CONN 28 SATA HDD 23
DCBATOUT
0.844~1.3V
High Definition Audio
ATA 66/100 44A
PATA ODD 23
AMOM ACPI 1.1
B
RJ11 HD Audio LPC I/F
PCB LAYER B
MODEM
CONN 29 TPM
CX20548 PCI/PCI BRIDGE LPC Bus L1: Signal 1
18,19,20,21 SLB9635TT
34
L2: GND
INTERNAL
L3: Signal 2
ARRAY MIC
HD AUDIO L4: Signal 3
MIC IN CODEC L5: GND
PCIE x 1
USB 2.0 x 1
PCIE x 1
CX20549-12Z PCIE+USB 2.0 KBC L6: VCC
29
LINE OUT ENE KB3910SF L7: Signal 4
Ricoh 31
L8: Signal 5
R5538
SPDIF 28 L9: GND
L10: Signal 5
Flash ROM
1MB 33
OP AMP Thermal
Mini-Card Mini-Card Capacity Touch Int.
APA2031 30 New Card CIR & Fan
A
28 802.11a/b/g26 WWAN26 Button32 Pad 32 KB32 A
G792 22
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH DOCK Title
SPEAKER 10/100
CRT MIC IN LINE OUT S/PDIF TVOUT Ethernet CIR Block Diagram
Size Document Number Rev
A3
Pamirs-Discrete SC
Date: Monday, December 18, 2006 Sheet 1 of 47
5 4 3 2 1
A B C D E
INTEL ICH8-M STRAP PIN 19,21 +RTCVCC +RTCVCC
4,5,6,7,9,10,11,19,21,37,47 1D05V_S0 1D05V_S0
3,7,10,21,38 1D25V_S0 1D25V_S0
Signal Usage/When Sampled Comment XOR Chain Entrance Strap 27 1D2V_LAN_S5 1D2V_LAN_S5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 ICH_RSVD
tp3 AZ_DOUT_ICH Description
28 1D5V_NEW_S0 1D5V_NEW_S0
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD
4 Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 0
1
1
0
Enter XOR Chain
Normal Operation(default)
5,10,17,19,20,21,26,28,38,47 1D5V_S0 1D5V_S0 4
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1
7,10,11,13,14,34,37,38 1D8V_S3 1D8V_S3
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. 27,28 2D5V_LAN_S5 2D5V_LAN_S5
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h) 29,30 3D3V_AUD_S0 3D3V_AUD_S0
Rising Edge of PWROK.
19,31,32,33,36,39,46 3D3V_AUX_S5 3D3V_AUX_S5
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should 27,28 3D3V_LAN_S5 3D3V_LAN_S5
not be pull HIGH.
3,4,7,10,11,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36,40,41,42,43,47 3D3V_S0 3D3V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space). 17,18,20,21,22,26,27,28,29,31,34,36,39,47 3D3V_S5 3D3V_S5
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable
Top-Swap bit until the system is rebooted high = default 22,26,29,31,34,36 5V_AUX_S5 5V_AUX_S5
without GNT3# being pulled down. BOOT BIOS Strap 16,23,32,33,34,36,37,38 5V_S3 5V_S3
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit 15,16,17,20,21,22,23,29,30,31,32,33,34,35,47 5V_S0 5V_S0
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI 16,21,34,37,40 5V_S5 5V_S5
1 1 LPC(Default)
Integrated VccSus1_05 17,39,46,47 AD+ AD+
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high 16,17,34,35,36,37,39,40,47 DCBATOUT DCBATOUT
SM_INTVRMEN High=Enable Low=Disable
sampled.
13,14,38 DDR_VREF_S0 DDR_VREF_S0
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05,VccCL1_05 VRM
integrated VccLan1_05VccCL1_05
7,13,14,38 DDR_VREF_S3 DDR_VREF_S3
3
LAN100_SLP VccCL1_05 VRM enable when sampled high LAN100_SLP High=Enable Low=Disable
/Disable. Always sampled. 22,31,33,39 KBC_3D3V_AUX KBC_3D3V_AUX
16 LCDVDD_S0 LCDVDD_S0
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8) 5,6,35 VCC_CORE_S0 VCC_CORE_S0
If sampled high, the system is strapped to the No Reboot Strap
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
TP3 XOR Chain Entrance. This signal should not be pull low unless using
Rising Edge of PWROK. XOR Chain testing.
GPIO33/
Internal Pull-Up.If sampled low,the Flash Descriptor
Flash Descriptor Security Security will be overidden.if high,the Security
INTEL ICH8-M INTEGRATED
HDA_DOCK_EN# Override Strap
Rising Edge of PWROK.
measures defined in the Flash Descriptor will be in
effect.
8.2K PULL HIGH PULL-UPS and PULL-DOWNS
This should only be used in manufacturing
environments
SIGNAL Resistor Type/Value
HDA_BIT_CLK PULL-DOWN 20K
HDA_RST# NONE
2 HDA_SDIN[3:0] PULL-DOWN 20K 2
HDA_SDOUT PULL-DOWN 20K
HDA_SYNC PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN GNT[3:0] PULL-UP 20K
CFG Strap LOW 0 HIGH 1 GPIO[20] PULL-DOWN 20K
CFG 5 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
DMI X 2 DMI X 4
CFG 8 LAN_RXD[2:0] PULL-UP 20K
Low Power PCI Express Normal Low Power mode
CFG 9 LDRQ[0] PULL-UP 20K
PCI Express Graphics Lane Reversal Normal Mode(Lanes
Lane Reversal number in order) LDRQ[1]/GPIO23 PULL-UP 20K
CFG 16
FSB Dynamic ODT Disabled Enabled PME# PULL-UP 20K
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane PWRBTN# PULL-UP 20K
CFG 20 Only PCIE or SDVO PCIE and SDVO are
Concurrent SDVO/PCIE is operation operation simultaneous SATALED# PULL-UP 20K
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present SPI_CS1# PULL-UP 20K
Present
SDVO Present SPI_CLK PULL-UP 20K
CFG 12 XOR/ALL-Z SPI_MOSI PULL-UP 20K
1 CFG 13
LL(00) Reserved
1
SPI_MISO PULL-UP 20K
LH(01) XOR Mode Enabled Wistron Corporation
HL(10) All Z Mode Enabled TACH_[3:0] PULL-UP 20K 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HH(11) Normal Operation Taipei Hsien 221, Taiwan, R.O.C.
SPKR PULL-DOWN 20K
Title
TP[3] PULL-UP 20K
Table of Content
USB[9:0][P,N] PULL-DOWN 15K Size Document Number Rev
A3
CL_RST# TBD Pamirs-Discrete SA
Date: Wednesday, November 01, 2006 Sheet 2 of 47
3D3V_S0 5 3D3V_S0_CK505 4 3 2 1
L21
1 2
MLB-160808-18-GP DY DY 3D3V_S0_CK505 1D25V_S0_CK505
1
1
1
1
1
1
1
1
C639 C337 C603 C594 C597 C630 C595 C600
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
X1
CLK_XTAL_IN 1 2 CLK_XTAL_OUT
X-14D31818M-40GP
1
1
D C328 C327
D
SC18P50V2JN-1-GP SC18P50V2JN-1-GP
2
2
U28
16
46
62
23
19
27
43
52
33
56
4
9 VDDPCI
VDDREF
VDD48
VDDPLL3
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDSRC
VDDCPU
61 CPU_BCLK 1 4 SRN0J-6-GP CLK_CPU_BCLK 4
1D25V_S0 1D25V_S0_CK505 CPUT0 CPU_BCLK#
CPUC0 60 2 3 CLK_CPU_BCLK# 4
RN30
L49 CLK_XTAL_IN 3 58 MCH_BCLK 1 4 SRN0J-6-GP CLK_MCH_BCLK 7
C332 SC4D7P50V2CN-1GP CLK_XTAL_OUT X1 CPUT1_F MCH_BCLK#
1 2 2 X2 CPUC1_F 57 2 3 CLK_MCH_BCLK# 7
RN33
MLB-160808-18-GP DY 1 2 54 CPU_XDP 1 4 SRN0J-6-GP CLK_CPU_XDP 4
CPUT2_ITP/SRCT8
1
1
1
1
1
1
1
1
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