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5 4 3 2 1
Intel (R) 845E Interactive
Client Reference Design
D
Revision X2 D
Last Change : 2002-09-26
# Schematic Page Prefix Netobject Changes from X1 to X2
1 COVER SHEET A_ CRITICAL ANALOG TRACES
1 All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity
2 BLOCK DIAGRAM AC_ AC97 SIGNAL
2 R712 changed from 10k to 15k to adjust voltage
3 BLOCK-POWER APIC_ APIC SIGNAL
3 PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5)
4 MECH-ROUTE AUD_ ANALOG AUDIO SIGNAL
4 Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error
5 NOTES
5 PU R758 added at CN34.7 (SYS_RESET#)
6 CPU-P4 BUS CK_ CLOCK SIGNAL 6 PU R759 added at U39.4 (VIDPWRGD)
7 CPU-P4 POWER 7 C717 changed from 4u7 to 1u
EEn_ SERIAL EEPROM LANn
8 CPU-ITP 8 R607 not populated
EN_ ENABLE FOR POWER SOURCES
9 R571 and R572 not populated (FWH Test Pins)
9 MCH-SYSBUS & CLOCK
F_ FLOPPY DISK SIGNAL 10 R585 and R586 not populated (for LVDS 18 Bit)
10 MCH-AGP & DDR
FWH_ FIRMWARE HUB SIGNAL 11 R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset
11 MCH-POWER
12 R501 and R494 not populated due to PCI config of LAN 82540
C
G_ AGP BUS SIGNAL C
12 CLK-ICS950201 13 U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25)
GND_ GND SIGNAL DERIVED
14 R496 changed to 4k7 and set to GND (PD M66EN)
13 DDR-DIMM 0 GND GND POWER
15 R525 and R499 is now populated
14 DDR-DIMM 1
H_ P4 HOSTBUS SIGNAL 16 R530 not populated due to wrong V_2V5LAN voltage
15 ICH4-SYSBUS & PCI 17 U20.G4 is now 51R Pulldown to GND
I2C_ I2C BUS SIGNAL
16 ICH4-LPC & IDE & USB 18 U20.H4 is now 33R Pullup to V_3V3LAN
IDE_ IDE SIGNAL
17 ICH4-POWER 19 AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4)
INT_ INTERRUPT SIGNAL
20 Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover
18 GLUE LOGIC
KB_ KEYBOARD SIGNAL 21 LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R)
19 SIO0-LPC47M107 22 R615 changed to 4K32 due to Cougar Bug
L_ LPC BUS SIGNAL
20 SIO1-LPC47N227 23 HW Rev changed to 2 at Glue Logic
LANn_ LAN CONTROLLER n SIGNAL
24 R373 is now populated with 10M
21 CONN-COM1/COM2/LPT LP_ LPT1284 SIGNAL
25 CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND
22 CONN-COM3/COM4/KBC
M_ MEMORY BUS SIGNAL 26 PU R761-R765 added to VID[0:4]
23 AC97-AD1885 MIDI_ MIDI SIGNAL 27 PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options)
MS_ MOUSE SIGNAL 28 HD-LED-power connected to V_5V0 instead of V_5V0SB
24 LAN-10/100/1000 BUS
29 PD R768 added to PS_ON
25 LAN-10/100/1000 CONN P_ PCI BUS SIGNAL
30 PU R769 added to U3.28 (PGOOD408#)
B 26 VGA-COUGAR-01 SPn_ SERIAL PORT n SIGNAL 31 PD R770, R771, R772 added to power enables (default off, if CPLD not configured) B
27 VGA-COUGAR-02 32 PD R773-R776 added to serial port shut down pins
USB_ USB PORT SIGNAL
28 VGA-COUGAR-03 33 Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs
V_ POWER 34 Removed R383, R384, R385
29 CONN-PCI
35 Added D25 to avoid crossvoltages from VGA Monitor
ZV_ ZV VIDEO PORT SIGNAL
30 CONN-01 IDE-FLOPPY 36 Added D26 to avoid crossvoltages LPT Port
37 Alternative population of L7 to L12 with resistors (0R)
31 USB0-USB1-LAN0
38 PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R
32 USB2-USB5
39 U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar
33 SYSTEM CONTROL 40 Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM
41 CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING)
34 DDR-POWER
42 V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25)
35 POWER
43 Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR
PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION
OR SAMPLE.
A No license, express or implied, by estoppel or otherwise, to any A
intellectual property rights is granted herein. Intel disclaims all
liability, including liability for infringement of any proprietary rights,
relating to use of information in this specification. Intel does not
warrant or represent that such use will not infringe such rights.
General Note:
Intel (R) 845E Interactive Client Reference Design
All Parts marked 'XXX1' will not be assembled in V1. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR
All Parts marked 'XXX2' will not be assembled in V2. MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE OR THE
Title
MISUSE OF THIS INFORMATION. COVER SHEET
Size Document Number Rev
* Other names and brands may be claimed as the property of others. C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1
Block Diagram
D D
CPU VRM CPU
Pg. 35 Clocking Glue Logic
ICS950201 Xilinx *
CK 408 Coolrunner
Pentium(R) 4 Processor
FCPGA478 Pg. 12 Pg. 18
ITP
Pg. 8 - Postcode decoding
Pg. 6, 7 - Speedstep logic
- Powerup sequencing
FSB 133MHz x4, 64b (4.3 GB/s)
1280x1024 @ 18Bit
LVDS max. 2 GB
Pg. 27
planar 845E MCH
Cougar 3DR *
DDR-DIMM
C C
i82845-E
DVI-I DVI/VGA BGA385 BGA593
16 MB int. mem. AGP 1.5V, 66MHz x4, 32b (1.1 GB/s) DDR SDRAM 2.5V, 266MHz, 64b (2.1 GB/s) DDR VR
Pg. 27
Pg. 34
I/O panel
Pg. 26, 27, 28
TV-OUT Pg. 9, 10, 11 Pg. 13
Pg. 27 PHY Pg. 14
I/O panel
i82562 Hub Interface 66MHz x4, 8b (266 MB/s)
RJ45
Pg. 31 Pg. 31
I/O panel
ICH4
PCI, 33MHz, 32b (132 MB/s) LPC 3.3V, 33MHz
B i82801 B
BGA421
SMB
5V PCI-Slot miniPCI-Slot LAN SYSMON FWH SIO SIO
Pg. 29 Pg. 29 LM87 8 Mbit LPC47N227 LPC47M107
Pg. 33 i82802AC
i82540
PLCC32
(optional Pg. 15, 16, 17 FAN
i82551/i82559)
ATA66/100
RJ45 PHOTO DIODE Pg. 33 Pg. 20 Pg. 19
Pg. 25 Pg. 24, 25
I/O panel USB2.0 AC'97
IDE0 Pg. 22 SERIAL2 SERIAL0 I/O panel Pg. 21
Pg. 30 LINE-IN I/O panel
USB AC97 Pg. 22 SERIAL3 SERIAL1 I/O panel Pg. 21
planar
LINE-OUT planar
Pg. 31, 32 AD1885 Pg. 20 FIR FDD planar Pg. 30
IDE1 HEADPHONE I/O panel
PARALLEL I/O panel Pg. 21
Pg. 30 3 * planar
MICRO I/O panel
planar K/B planar Pg. 22
A
2 * I/O panel Pg. 23 CD-ROM planar A
2 * I/O panel, powered MOUSE planar Pg. 22
2 * planar
Intel (R) 845E Interactive Client Reference Design
Title
BLOCK-DIAGRAM
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 2 of 35
5 4 3 2 1
5 4 3 2 1
SLP_S3#
ATX POWER ATX 12V
D 12V 5V 5VSB 3V3 12V D
CPU
VRM MODULE VCCP
MIC5284 VCC_1V2VID
CLK
VCC_CLK
MCH
VTT
C
ISL6225 A VCC_1V5 C
LTC1117 VCC_1V8
VCC_DDR
DIMM
ISL6225 A VCC_DDR
SLP_S4#
VCC_REF
SLP_S3# B VCC_TERM
B B
ICH4
VCC_5V0SUS
LTC1117 VCC_3V3SUS
LTC1117 VCC_1V5SUS
VCC_1V8S
VCC_1V5S
VCC_3V3S
VCC_5V0S
A A
COUGAR *
ISL6225 B V_3V3AGP
Intel (R) 845E Interactive Client Reference Design
Title
BLOCK-POWER
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 3 of 35
5 4 3 2 1
5 4 3 2 1
B1 B4 B7
BOHR4.0 BOHR4.0 BOHR4.0
Mx
Mx
Mx
M29 M10 M1
M7
B2
BOHR4.0
B5
BOHR4.0
B8
BOHR4.0 FWH B4441000.01
Mx
Mx
Mx
D D
1
2
3
4
MACADRESS BIOS IN P4_RETENT
82802AC
B3 B9 Firmware-Hub
BOHR4.0 BOHR4.0 M2
Mx
Mx
M30 BRD1 M23 M24 M25 M26
SM02/RD SM02/RD SM02/RD SM02/RD
1
2
3
4
5
6
7
8
MACADRESS PCB BGA593A/COOL
XXX1 B444B
XXX2
V_CORE V_CORE V_CORE V_CORE V_CORE
M31
M E C H
DK1 DK2 DK3 DK4 DK5 BAT_CR2032
DK204060 DK204060 DK204060 DK204060 DK204060 M11 M12
M32
HS_MCH_PIN_FIN HS_MCH_INTERFACE
V_CORE V_CORE V_CORE V_CORE V_CORE M E C H XXX1 XXX1
XXX2 XXX2
JMP_2mm54 M15 M16 M17
HS_MCH_LEVER HS_MCH_CLIP HS_MCH_PORON
DK6 DK7 DK8 DK9 DK10 XXX1 XXX1 XXX1
DK204060 DK204060 DK204060 DK204060 DK204060 XXX2 XXX2 XXX2
V_CORE V_CORE V_CORE V_CORE V_CORE
C C
DK11 DK12 DK13 DK14 DK15
DK204060 DK204060 DK204060 DK204060 DK204060
V_CORE V_CORE V_CORE
DK16 DK17 DK18
DK204060 DK204060 DK204060
MARKE1 MRKF1
MARKETOP MARKFPIT
MARKE2
MARKETOP
MARKE3
MARKETOP
B B
TP1 TP2 TP3 TP4
GND GND GND GND
A A
Intel (R) 845E Interactive Client Reference Design
Title
MECH-ROUTE
6..8,11,17,33,35 V_CORE V_CORE
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 4 of 35
5 4 3 2 1
5 4 3 2 1
INPUT DERIVED VOLTAGES --> I2C DEVICES
VOLTAGES
DEVICE ADDRESS BUS
V_12V0VRM V_12V0VRMF V_CORE V_VCCA
V_VCCIOPLL CLOCK GENERATOR 1101001x SM BUS
SO-DIMM0 1010000x SM BUS
V_12V0 V_FAN1 V_12USB2 V_12VAUD SO-DIMM1 1010001x SM BUS
V_FAN1S V_12USB2F V_AUDOUT ICH4 SLAVE 1000100x SM LINK
V_FAN1SF V_12USB2S V_5VAUD LAN CONTROLLER N/A SM LINK
D V_FAN2 V_12USB3 V_BLI LM87 HW MONITOR 0101110x SM BUS D
V_FAN2S V_12USB3F
V_FAN2SF V_12USB3S
V_5V0SB V_3V3SB V_3V3LAN V_1V5LAN
V_3V3LAN0 V_2V5LAN
PCI/AGP DEVICES
V_1V5SB
V_KB DEV IDSEL DEVICE IRQ REQ/GNT
V_KBF
00 AD16 COUGAR AGP A AGP
V_DDR V_DDRREF 01 AD17 LAN10/100/1000T G 4
02 AD18
V_USB0 V_USB0X V_DDRVTT 03 AD19
V_USB1 V_USB1X 04 AD20
V_USB2 V_USB2X 05 AD21
V_5V0 06 AD22
V_USB3 V_USB3X
V_USB4 V_USB4X 07 AD23
V_USB5 V_USB5X 08 AD24 INTERNAL LAN N/A N/A
09 AD25 MINI PCI SLOT E-F 3
10 AD26 STD PCI SLOT A-B-C-D 0
V_1V5 V_1V5A1 V_HVDD 11 AD27 RISER SLOT1 B-C-D-A 0
C
V_1V5A2 V_ICHPLL 12 AD28 C
13 AD29 RISER SLOT2 C-D-A-B 1
V_3V3AGP V_2V5_LVD V_2V5_LVD1 V_PLLVDD 14 AD30
V_LVDD1 V_2V5_LVD2 15 AD31 RISER SLOT3 D-A-B-C 2
V_LVDD2 V_CVDD
V_2V0_2V5 V_VDD1
ICH4 GPIOs
V_2V5_VDD V_VDD2
V_VDD3 GPIO DEVICE SIGNAL NAME
V_VCC1 V_DL_CL GPI6 SUPER I/O 0 SIO0_SMI#
V_AVCC1 V_DL_CLF GPI7 SUPER I/O 1 SIO1_SMI#
V_AVDD GPI8 SUPER I/O 0 SIO0_PME#
V_PVCC1 V_FPVDD
V_VREF_SII GPI12 SUPER I/O 1 SIO1_PME#
V_TVDD GPI13 CPLD XC_GPIO2
V_DBL V_VPVDD GPIO25 LAN0 KINNERETH LAN0_ENA
GPIO27 MINI PCI MPCI_ACT#
V_5DVI V_5V0CF V_AMP GPIO28 CPLD XC_GPIO1
V_PIDE V_5DVIF V_AMPIN GPIO32 PRIMARY IDE IDE_PPDIAG#
V_SIDE V_IOLAN V_AMPINX GPIO33 SECONDARY IDE IDE_SPDIAG#
B V_AMPOUT GPIO34 POWERED USB USB_PWR2ENA# B
V_FIR V_GAME
V_IR V_GAMEF V_5V0REF GPIO35 POWERED USB USB_PWR3ENA#
GPIO36 FIRMWARE HUB FWH_WP#
V_3V3 V_1V2VID GPIO37 FIRMWARE HUB FWH_TBL#
V_1V8 GPIO38 PCI RISER RISER_ID1
V_CLK GPIO39 PCI RISER RISER_ID2
GPIO40 AUDIO AMPLIFIER AMP_SHDN
V_3V3SB GPIO41 PCI RISER NOGO
GPIO42 PCI SLOT P_PRSNT1#
GPIO43 PCI SLOT P_PRSNT2#
V_RTC
V_BAT
V_RTCBIAS
V_-12V0
V_-5V0
POWER STATES
A A
ON IN STATE POWER PLANE
S5 (SOFT OFF) V_*SB, V_KB, V_*LAN, V_USB*
Intel (R) 845E Interactive Client Reference Design
S3 (SUS. TO RAM) V_DDR, V_DDRREF
Title
NOTES
S0 (FULL ON) OTHERS Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 5 of 35
5 4 3 2 1
5 4 3 2 1
H_D[0..63]
H_D[0..63] 9
U1A SW478/S1
H_A#[3..31] SPAREPIN AB1 AA24 H_D63
9 H_A#[3..31] A35# D63# H_D62
SPAREPIN Y1 AA22
SPAREPIN A34# D62# H_D61
W2 A33# D61# AA25
SPAREPIN V3 Y21 H_D60
H_A#31 A32# D60# H_D59
U4 A31# D59# Y24
H_A#30 T5 Y23 H_D58
H_A#29 A30# D58# H_D57
W1 A29# D57# W25
H_A#28 R6 Y26 H_D56
D H_A#27 A28# D56# H_D55 D
V2 A27# D55# W26
H_A#26 T4 V24 H_D54
H_A#25 A26# D54# H_D53
U3 A25# D53# V22
H_A#24 P6 U21 H_D52
H_REQ#[0..4] H_A#23 A24# D52# H_D51
9 H_REQ#[0..4] U1 A23# D51# V25
H_A#22 T2 U23 H_D50
H_A#21 A22# D50# H_D49
R3 A21# D49# U24
H_A#20 P4 U26 H_D48
H_A#19 A20# D48# H_D47
P3 A19# D47# T23
H_A#18 R2 T22 H_D46
H_A#17 A18# D46# H_D45
T1 A17# D45# T25
H_A#16 N5 T26 H_D44
H_A#15 A16# D44# H_D43
N4 A15# D43# R24
H_A#14 N2 R25 H_D42
H_A#13 A14# D42# H_D41
M1 A13# D41# P24
H_ADSTB#[0..1] H_A#12 N1 R21 H_D40
9 H_ADSTB#[0..1] H_A#11 A12# D40# H_D39
M4 A11# D39# N25
H_A#10 M3 N26 H_D38
H_A#9 A10# D38# H_D37
L2 A9# D37# M26
H_A#8 M6 N23 H_D36
H_A#7 A8# D36# H_D35
L3 A7# D35# M24
V_CORE V_CORE H_A#6 K1 P21 H_D34
H_A#5 A6# D34# H_D33
L6 A5# D33# N22
H_A#4 K4 M23 H_D32
H_A#3 A4# D32# H_D31
K2 A3# D31# H25
K23 H_D30
D30# H_D29
D29# J24
H_REQ#4 H_D28
R2
R3
R4
R5
H3 REQ4# D28# L22
H_REQ#3 J3 M21 H_D27
H_REQ#2 REQ3# D27# H_D26
J4 REQ2# D26# H24
H_REQ#1 K5 G26 H_D25
H_REQ#0 REQ1# D25# H_D24
J1 REQ0# D24# L21
H_D23
301RA
62RA
51RA
62RA
D23# D26
F26 H_D22
H_ADSTB#1 D22# H_D21
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