Service Manuals, User Guides, Schematic Diagrams or docs for : . Various Div Laptop Schema`s Toshiba Satellite_M50_Compal_LA-2861
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A B C D E
1 1
HAZ00/HTW01
2 2
LA-2861 REV 1.0 Schematic
3 3
UFC-PGA Dothan/ RC410MD(RC410MB)/ SB450
2005-07-11 Rev.1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
Black Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HAZ00/BL10E (LA2861) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 04, 2005 Sheet 1 of 42
A B C D E
A B C D E
HAZ00 & HTW01 LA-2861 FUNCTION BLOCK DIAGRAM
4
INTEL 4
Thermal Sensor Clock Generator FANController
Celeron 479 pin ADM1032ARM
ICS951411AGT
CPU VID PAGE 33
PAGE 4,5,6 PAGE 5 PAGE 11 PAGE 5 RTC Battery PAGE 14
CRT Conn.
FSB
400MHz DC/DC Interface
page 13 PAGE 34
LID/Kill Switch
LCD Conn Power Buttom
page 12 PAGE 31
ATI-RC410MB 400/533/667MHz
(1.8V) SO-DIMM x 2(DDRII)
Memory Bus BANK 0,1,2,3 PAGE 9,10
LVDS & TV-OUT Conn. VGA M10P Embeded
page 12 DCIN&DETECTOR
3 PAGE 35 3
707 pin BGA
PAGE 6,7,8
BATT CONN/OTP
A-Link Express x 4
PAGE 36
Bandwidth 500MB
2.5GHz(1.2V)
CHARGER PAGE 37
480MHz(5V) USB 2.0 Port *3
0,2,4 PAGE 36
3V/5V/12V PAGE 38
Primary DDR_1.8V/0.9VEP
ATA-100 (5V) PAGE 40
IDE HDD
PCI BUS
33MHz (3.3V) ATI-SB450 PAGE 26
1.8VCORE PAGE 39
564 pin BGA Secondary
2 ATA-100 (5V) 2
HAZ00 IDE ODD 1.5V/PROCHOT PAGE 40
Mini PCI PAGE 21,22,23,24,25 PAGE 26
CARDBUS TSB43AB21
FOR WLAN
CB1410 CPU_CORE
PAGE 22 PAGE 23 LPC BUS 33MHz (3.3V) PAGE 41
PAGE 20
BL10E IDE ODD
PAGE 26
Embedded
LAN
CARD BUS 1394-Port RTL8100CL Controller AC-LINK
14.318MHz(3.3V)
SOCKET PAGE 22 PAGE 19 ENE KB910PAGE 29 AC97 CODEC Audio Amplifier
ALC 250 APA2068 PAGE 25
PAGE 21 PAGE 24
RJ-45
PAGE 19
MDC
BIOS(1M) Scan KB Connector
PAGE 33
& I/O PORT PAGE 30
1 1
PAGE 30
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
Black Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HAZ00/BL10E (LA2861) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 04, 2005 Sheet 2 of 42
A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) ON ON ON
1 B+ AC or battery power rail for power circuit. ON ON ON S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+CPUVID 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
+VGA_CORE 1.0V/1.2V switched power rail for VGA chip ON OFF OFF S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+1.2VS 1.2VS for PCI-Express ON OFF OFF
+0.9VS 0.9V switched power rail ON OFF OFF
+1.5VS DOTHAN B ON OFF OFF
Board ID Table for AD channel
+1.8VS 1.8VS switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON* Vcc 3.3V +/- 5%
+1.8V 1.8V power rail ON ON OFF Ra 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+12VALW 12V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
2 2
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts Board ID PCB Revision
TI 1410 AD20 2 PIRQA/PIRQB 0 0.1, 0.2
LAN A D22 1 PIRQG 1 0.3
Mini-PCI(WLAN) AD18 3 PIRQF/PIRQG 2 1.0
1394 AD16 0 PIRQA 3
4
5
3 3
6
7
EC SM Bus1 address EC SM Bus2 address SKU ID SKU Status HDD Password
Device Address Device Address
0 0 NO
Smart Battery 0001 011X b ADM1032 1001 110X b
1 1 Yes
2
3
4
5 1 Buttons
6
7 7 Buttons
SB450 SM Bus address
Device Address
4 4
Clock Generator 1101 001Xb
(ICS951413BGLFT)
DDR DIMM0 1010 0100b A4
DDR DIMM1 1010 0110b A6 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HAZ00/BL10E (LA2861) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 04, 2005 Sheet 3 of 42
A B C D E
5 4 3 2 1
+3VS
H_D#[0..63]
H_D#[0..63] 6
1
1
JP19A
C502 R303
H_A#[3..31] H_A#3 P4 A19 H_D#0 0.1U_0402_16V4Z @ 10K_0402_5%
6 H_A#[3..31]
H_REQ#[0..4]
H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H_D#1
H_D#2
2
6 H_REQ#[0..4] V3 A22 1
2
H_A#6 A5# D2# H_D#3 C503 U26
R3 A6# D3# B21
H_RS#[0..2] H_A#7 V2 A24 H_D#4 THERMDA 2 1
6 H_RS#[0..2] A7# D4# D+ VDD1
H_A#8 W1 B26 H_D#5 2200P_0402_50V7K
H_A#9 A8# D5# H_D#6 2 THERMDC
D T4 A9# D6# A21 3 D- ALERT# 6 D
H_A#10 W2 B20 H_D#7
H_A#11 A10# D7# H_D#8
Y4 A11# D8# C20 28 EC_SMB_CK2 8 SCLK THERM# 4
H_A#12 Y1 B24 H_D#9
H_A#13 A12# D9# H_D#10
U1 A13# D10# D24 28 EC_SMB_DA2 7 SDATA GND 5
H_A#14 AA3 E24 H_D#11
H_A#15 A14# D11# H_D#12
Y3 A15# D12# C26
H_A#16 AA2 B23 H_D#13 ADM1032ARM_RM8
H_A#17 A16# D13# H_D#14
AF4 A17# D14# E23
H_A#18 AC4 C25 H_D#15
H_A#19 A18# D15# H_D#16
AC7 A19# D16# H23
H_A#20 AC3 G25 H_D#17 +1.05VS +CPU_CORE
H_A#21 A20# D17# H_D#18
AD3 A21# D18# L23
H_A#22 AE4 M26 H_D#19
A22# D19#
1
1
H_A#23 AD2 H24 H_D#20
H_A#24 A23# D20# H_D#21 R68 R69
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22 @ 47K_0402_5% 47K_0402_5%
H_A#26 A25# D22# H_D#23
AD5 A26# D23# J23
H_A#27 AE2 M23 H_D#24
MAINPWON 15,34,35,37,38
2
2
H_A#28 A27# D24# H_D#25 +1.05VS
AD6 A28# D25# J25
1
H_A#29 AF3 L26 H_D#26 C
A29# D26#
470_0402_5%
H_A#30 AE1 N24 H_D#27 1 2 2
A30# D27#
2
H_A#31 AF1 M25 H_D#28 B Q22
A31# D28# H_D#29 C260 E 2SC2411K_SC59
H26
3
D29#
R172
H_REQ#0 R2 N25 H_D#30 @ 0.1U_0603_25V7K H_DPSLP#
H_REQ#1 REQ0# D30# H_D#31
P3 REQ1# D31# K25
1
H_REQ#2 T2 Y26 H_D#32
1
H_REQ#3 REQ2# D32# H_D#33 Q26
P1 REQ3# D33# AA24 +1.05VS 1 2 2
H_REQ#4 T1 T25 H_D#34 R67 R166 MMBT3904_SOT23
REQ4# D34#
1
U23 H_D#35 56_0402_5% 470_0402_5%
3
D35# H_D#36 H_THERMTRIP# Q27
6 H_ADSTB#0 U3 ADSTB0# D36# V23 11,14,40 CPU_STP# 2 1 2
C AE5 R24 H_D#37 C
6 H_ADSTB#1 ADSTB1# D37#
R26 H_D#38
3
D38# H_D#39
D39# R23
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41 MMBT3904_SOT23
A15 ITP_CLK1 D41# U26
V24 H_D#42
D42# H_D#43
11 CLK_BCLK B15 BCLK0 D43# U25
B14 HOST CLK V26 H_D#44
11 CLK_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
D46# AA26
Y25 H_D#47 +1.05VS
D47# H_D#48
6 H_ADS# N2 ADS# D48# AB25
L1 AC23 H_D#49
6 H_BNR# BNR# D49#
J3 AB24 H_D#50 H_FERR# R72 2 1 56_0402_5%
6 H_BPRI# H_BR0# BPRI# D50# H_D#51
N4 BR0# D51# AC20
L4 AC22 H_D#52 PREQ# R77 2 1 @ 56_0402_5%
6 H_DEFER# DEFER# D52# H_D#53
6 H_DRDY# H2 DRDY# D53# AC25
K3 AD23 H_D#54 H_DPSLP# R62 1 2 200_0402_5%
6 H_HIT# HIT# D54#
K4 CONTROL GROUP AE22 H_D#55
6 H_HITM# HITM# D55#
H _IERR# A4 AF23 H_D#56 H_BR0# R70 1 2 200_0402_5%
IERR# D56# H_D#57
6 H_LOCK# J2 LOCK# D57# AD24
H_RESET# B11 AF20 H_D#58 H_DPRSTP# R71 2 1 @ 56_0402_5%
6,14 H_RESET# RESET# D58# H_D#59
D59# AE21
AD21 H_D#60 ITP_TDI R79 2 1 150_0402_5%
H_RS#0 D60# H_D#61
H1 RS0# D61# AF25
H_RS#1 K1 AF22 H_D#62 ITP_TDO R78 2 1 @ 54.9_0402_1%
H_RS#2 RS1# D62# H_D#63
L2 RS2# D63# AF26
M3 H_RESET# R63 2 1 @ 54.9_0402_1%
6 H_TRDY# TRDY#
D25 ITP_TMS R64 2 1 40.2_0402_1%
DINV0# H_DINV#0 6
DINV1# J26 H_DINV#1 6
B PROCHOT# R66 56_0402_5% B
C8 BPM0# DINV2# T24 H_DINV#2 6 2 1
B8 BPM1# DINV3# AD20 H_DINV#3 6
A9 H _IERR# R75 2 1 56_0402_5%
BPM2#
C9 BPM3#
C23 H_PWRGOOD R82 2 1 200_0402_5%
DSTBN0# H_DSTBN#0 6
ITP_DBRRESET# A7 K24
DBR# DSTBN1# H_DSTBN#1 6
M2 W25 H_CPUSLP# R81 1 2 200_0402_5%
6 H_DBSY# DBSY# DSTBN2# H_DSTBN#2 6
H_DPSLP#
H_DPRSTP#
B7
G1
DPSLP# DSTBN3# AE24
C22
H_DSTBN#3 6 Place Caps Close to CPU Socket
DPRSTP# DSTBP0# H_DSTBP#0 6
C19 L24 C263 1 2 180P_0402_50V8J H_INIT#
6 H_DPWR# DPWR# DSTBP1# H_DSTBP#1 6
A10 PRDY# MISC DSTBP2# W24 H_DSTBP#2 6
PREQ# B10 AE25 C255 1 2 180P_0402_50V8J H_A20M#
PREQ# DSTBP3# H_DSTBP#3 6 +3VS
PROCHOT# B17 PROCHOT# C264 1 H_CPUSLP#
2 180P_0402_50V8J
H_PWRGOOD E4
14 H_PWRGOOD PWRGOOD
H_CPUSLP# A6 C254 1 2 180P_0402_50V8J H_INTR ITP_DBRRESET# R76 2 1 @ 150_0402_5%
14 H_CPUSLP# SLP#
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