Service Manuals, User Guides, Schematic Diagrams or docs for : . Various Div Laptop Schema`s hp_nx6320
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5 4 3 2 1
OT1 BLOCK DIAGRAM 14.318MHz
CPU CORE CPU Thermal
P37 Clock Generator
D Intel ULV Peutium-M / ULV Celeron-M Sensor
MAX6657 P5 ICS CK410-M
D
+1.05V/+1.5V_A
ULV Yonah / ULV Celeron P4
P36
479 Pins XDP
(Micro-FCBGA) P5,6 CONN60_ITP-XDP
P5
DC/DC 3V & 5V P34
HyperThansport I/O BUS
1.8V/SMDDR_VTERM/SMDR_VREF
P35 400MHZ Cable Docking
BATT CHARGER LVDS
LCD Panel 1 TO 4 USB HUB
MAX8724/1908 P33 P18 Singal Channel DDR2
Calistoga-GM DDR2-SODIMM1 P13
LINE IN
DISCHARGE/+2.5V R.G,B LINE OUT
P32
CRT port P26
1466 uFCBGA
RJ45
CRT PORT
P7,8,9,10,11,12 SVIDEO OUT
C
POWER JACK C
P31
32.768KHz
DMIx2
PATA PCI BUS
HDD (1.8 inch)P27 24.576MHz 48MHz 25MHz
ICH7-M
DVD-ROM P27
652 BGA
PCI-E LAN
MINI CARD PCMCIA Controller
USB 2.0 SOCKET P19 Broadcom
USB PORT 0 P28
TI 7612 P20,21 BCM5788 P22
P14,15,16,17
USB PORT 1(POWER SPI SYSTEM
USB) P28 BIOS SPI PCMCIA Slot RJ45
P31
B / Smart Card P21 P22 B
Bluetooth Module P28
Azalia
Audio AMP
AUDIO
FingerPrint CODEC TPA6211A JACK
P28 AD1981HD P23,24 P24 P24
3.3V LPC, 33MHz
32.768KHz 32.768KHz
RJ11
MODEM
JACK
MDC 1.5 P29 P29
SYSTEM
TPM (1.2) BIOS
SMSC1021
P28 FWH P30
100 Pins TQFP
A A
P25
PROJECT : OT1
FAN Track Keyboard Quanta Computer Inc.
Size Document Number Rev
P29 PointP29 P29 Custom System Block Diagram 1A
Date: Friday, July 29, 2005 Sheet 1 of 38
5 4 3 2 1
5 4 3 2 1
INDEX Power & Ground
Control
Pg# Description NOTE Label ACTIVE Description
Signal
VIN S0, S3, S4, S5 AC ADAPTER (19V)
1 Schematic Block Diagram
MBAT S0, S3, S4, S5 MAIN BATTERY + (10~17V)
2 System Information
D D
VCCRTC S0, S3, S4, S5 RTC & KBC POWER (3_3V)
3 System Power Block Diagram
+15V S0, S3, S4, S5 +15V
4 CLOCL GENERATOR
CPU_CORE S0 CPU CORE POWER (1.25/1.15V) VRON
5-6 Intel ULV Peutium-M / ULV Celeron-M
+1.05V S0 FSB POWER (1.05V) VRON
7-12 Calistoga-GM
13 DDR II SO-DIMM
+3V S0 MAIND
14-17 ICH7-M
3VSUS S0, S3 SUSON
18 LCD CONNECTOR / LCD PWR
3V_S5 S0, S3, S4, S5 S5_ON
19 MINI CARD
3VPCU S0, S3, S4, S5 ALWAYS POWER (3V)
20-21 CARDBUS CONTROLLER
+5V S0 MAIND
22 GIGA-LAN
C C
5VSUS S0, S3 SUSON
23-24 AUDIO CODEC / AUDIO JACK
5V_S5 S0, S3, S4, S5 S5_ON
25 KBC
5VPCU S0, S3, S4, S5 ALWAYS POWER (5V)
26 CRT PORT
+1.5V S0 MAIND
27 HDD / CD-ROM
1.5V_S5 S0, S3, S4, S5 S5_ON
28 USB,BLUE TOOTH,FINGER PRINT, MDC,TPM
1.8VSUS S0, S3 DDR CORE POWER SUSON
29 FAN,KB,LEDs,TRACK POINT
+2.5V S0 MAINON
30 POWER SEQUENCE,BIOS
SMDDR_VTERM S0 DDR COMMAND & CONTROL PULL UP POWER MAINON
31 CABLE DOCKING
SMDDR_VREF S0, S3 DDR REF POWER SUSON
32 DISCHARGE,+2.5V
VDDA S0 AUDIO ANALOG POWER (5V) MAINON
B 33 CHARGE(MAX8724/1908) B
34 SYSTEM POWER(3V/5V)
GND ALL PAGES DIGITAL GROUND
35 SYSTEM POWER(1.8V/0.9V)
36 SYSTEM POWER(1.05V/1.5V) AGND AUDIO GND
37 CPU POWER T-GND AUDIO JACK GND
38 CHANGE HISTORY
6260AGND CPU ANALOG GROUND
PCI DEVICES IRQ ROUTING PCB STACK UP SM BUS
DEVICE IDSEL # REQ/GNT # PCI_INT LAYER 1 : TOP DEVICE ADDRESS BUS
GBIT ETHERNET AD16 0 B LAYER 2 : GND
CLOCK GENERATOR D2H (ICH6) PCLK_SMB, PCLK_SMB
A
LAYER 3 : IN1 A
CardBus AD25 1 C,D,E
LAYER 4 : IN2 DDR II A0H (ICH6)PCLK_SMB, PCLK_SMB
LAYER 5 : VCC
LCD EDID TBD GMCH
LAYER 6 : IN3 PROJECT : OT1
LAYER 7 : GND CHARGER 16H (KBC) MBDATA,MBCLK Quanta Computer Inc.
LAYER 8 : BOT Size Document Number Rev
CPU THERMAL SENSOR 98H (KBC) MBDATA,MBCLK Custom System Information 1A
Date: Friday, July 29, 2005 Sheet 2 of 38
5 4 3 2 1
5 4 3 2 1
S5_ON
S.W
SYSTEM POWER BLOCK DIAGRAM MOS-FET 3V_S5
MAINON
D D
S.W SC4215 +2.5V
Adaptor MOS-FET MAIND
S.W +3V
3VPCU
ALWAYS MOS-FET
VIN
3VSUS
MAX1999 SUSD
MAIND
5VPCU S.W +5V
ALWAYS
C
VIN MOS-FET C
5VSUS
SUSD
+15V S5_ON
S.W
MOS-FET 3V_S5
CHARGER
SUSON
MAX8724/1908 MAINON
MAX1992 SMDDR_VTERM
1.8VSUS TPS51100
SMDDR_VREF
MAINON
B B
1.05V
MAX1540 MAIND
VIN
S.W 1.5V_A S.W
BATTERY MOS-FET +1.5V
MOS-FET
S5_ON
VRON
KBC_PW_ON S5_ON S5_OND
VIN TC7SH08FU DISCHARGE
SLP_S5# SUSON SUSD
CPU_VID[0..5] TC7SH08FU DISCHARGE
A A
HWPG MAX1907 CPU_CORE SLP_S3# MAINON MAIND
TC7SH08FU DISCHARGE
DPRSLPVR
STP_CPU#
PROJECT : OT1
Quanta Computer Inc.
Size Document Number Rev
C System Power block diagram 1A
Date: Friday, July 29, 2005 Sheet 3 of 38
5 4 3 2 1
1 2 3 4 5 6 7 8
(5,9,10,11,13,14,15,16,17,18,19,21,22,23,25,26,27,28,29,30,31,32,34,37)
(5,6,7,9,10,11,14,17,31,36)
+3V
+1.05V
Place these termination to close CK410M.
L11
+3V CLKVDD C105 CLK_VDDA
ACB2012L-120 XIN DB2 stage:change RP7,RP11,RP22,RP14,RP12 to 22 ohm
120 ohms@100Mhz
C135 C148 C150 C157 C138 15P 7/15/2005
2
10U 0.1U 0.1U 0.1U 0.1U CL=20pF
37
38
Y6 U21
14.318MHZ 50 52 14M_REF R126 33R
VDDA
VSSA
XTAL_IN REF 14M_ICH (16)
C106 RP7 22X2
1
R139 2.2R XOUT 49 44 RHCLK_CPU 1 2 CLK_CPU_BCLK (5)
CLK_VDDA XTAL_OUT CPU0 RHCLK_CPU#
CPU0# 43 3 4 CLK_CPU_BCLK# (5)
A DB2 stage:change C105,C106 to 15P 15P RP11 22X2 A
(37) VR_PWRGD_CK410# 10 41 RHCLK_MCH 1 2 CLK_MCH_BCLK (7)
C149 C446 C144
7/12/2005 VTT_PWRGD#/PD CPU1 RHCLK_MCH#
(16) PM_STPPCI# 55 PCI_STOP# CPU1# 40 3 4 CLK_MCH_BCLK# (7)
10U 0.1U .01U (16) PM_STPCPU# 54 RP17 *33X2
CPU_STOP# RHCLK_XDP
CPU2_ITP/SRC7 36 1 2 CLK_XDP (5)
reserve for LP218 35 RHCLK_XDP# 3 4
CPU2#_ITP/SRC7# CLK_XDP# (5)
R131 *10K
+3V
L7 SMBCK 46 33 218REQA# R361 0
CLKVDD1 CLK48M SMBDT SCLK SRC6/CLKREQA#
+3V LP218 NC
(21) CLK48M R132 12.1/F 47 32 R365 10K
+3V SDATA SRC6#/CLKREQB#
ACB2012L-120 RP21 *33X2 CLKREQB# (19)
120 ohms@100Mhz (16) CLKUSB_48 CLKUSB_48 R129 12.1/F CG_BSEL0 12 CK-410M 31 RSRC5 1 2 CLK_PCIE_XDP (5)
C119 C108 C104 R135 0 CG_BSEL1 FSA/USB_48 SRC5 RSRC5#
16 FSB/TEST_MODE/GND SRC5# 30 3 4 CLK_PCIE_XDP# (5)
0.1U 0.1U 10U CG_BSEL2 R345 4.7K R_CG_BSEL2 53 RP22 22X2
R119 33R FSC/TEST_SEL RSRC4
(25) 14M_KBC SRC4/SATA 26 3 4 CLK_PCIE_MINI (19)
CLK_VDDREF 48 27 RSRC4# 1 2 CLK_PCIE_MINI# (19)
CLKVDD VDD_REF SRC4#/SATA#
42 VDD_CPU
24 RSRC3 R141 0
CLKVDD1 SRC3/GND RSRC3#
R130 2.2R 1 VDD_PCI_1 SRC3#/GND 25 R142 0 LP218 NC
CLK_VDD48 7 RP18 33X2
VDD_PCI_2 RSRC_ICH
SRC2 22 3 4 CLK_PCIE_ICH (15)
CLKVDD 21 23 RSRC_ICH# 1 2
VDD_SRC0 SRC2# CLK_PCIE_ICH# (15)
C131 C139 28 RP14 22X2
0.1U 4.7U/10V VDD_SRC1 RSRC_MCH
DB 2 stage:mount R357 34 VDD_SRC2 SRC1 19 3 4 CLK_PCIE_3GPLL (9)
7/15/2005 20 RSRC_MCH# 1 2
SRC1# CLK_PCIE_3GPLL# (9)
CLK_VDD48 11 RP12 22X2
VDD_48 RDREFSSCLK
SRC0 17 3 4 DREFSSCLK (9)
Iref=2.32mA, R357 4.75K/F IREF 39 18 RDREFSSCLK# 1 2
IREF SRC0# DREFSSCLK# (9)
R127 1R
CLK_VDDREF Ioh=4*Iref 9 208REQA# R128 10K
B PCIF1/CLKREQA# R_PCLK_PCI R120 12.1/F
B
PCI5 5 PCLK_FWH (30)
RP8 4 R_PCLK_KBC R115 12.1/F
GND_PCI_1
GND_PCI_2
PCI4 PCLK_KBC (25)
GND_SRC
GND_CPU
C133 DREFCLK R_DOT96 R_PCLK_6611 R112 33R
GND_REF
(9) DREFCLK 1 2 14 DOT96 PCI3 3 PCLK_6611 (20)
GND_48
0.1U DREFCLK# 3 4 R_DOT96# 15 56 R_PCLK_LAN R116 33R
(9) DREFCLK# DOT96# PCI2 PCLK_LAN (22)
8 R_PCLK_ICH R125 33R
PCIF0/ITP_EN PCLK_ICH (15)
DB2 stage:change RP8 to 22 ohm 22X2
R117 12.1/F PCLK_DBP (19)
7/12/2005 ICS9LP208AGLFT R118 12.1/F
ICS9LP208/ICS954218 PCLK_TPM (28)
13
51
2
6
29
45
+3V
U20 250mA ( MAX. ) +3V
FSC FSB FSA CPU SRC PCI
1
VR_PWRGD_CK410# 2
5 SMbus address D4
1 0 1 100 100 33 DOTHAN FSB 400 (37) VR_PWRGD_CK410# +3V
3 4 VR_PWRGD_CK410 VR_PWRGD_CK410 (16) SRC0 TO 100M
0 0 1 133 100 33 DOTHAN FSB 533 R122
SN74LVC1G04DCKR R_PCLK_ICH R124 10K *10K
0 1 1 166 100 33 14M_REF
+3V
0 1 0 200 100 33
0 0 0 266 100 33
R123 SRC0 TO 96M
1 0 0 333 100 33 10K
Q13 R114 R113
2
1 1 0 400 100 33 2N7002E 10K 10K
EMI
1 1 1 RESERVED SMBDT
(16) PDAT_SMB 3 1 SMBDT (13,19,26) 48MHZ
C
ICS9LP208 should be removed C
* Frequence select by CPU auto sense. +3V
To ICH6-M To DDR-SODIMM CLKUSB_48 C128 *10P RP6 *49.9/FX2
Q12 CLK_CPU_BCLK 1 2
2
2N7002E CLK_CPU_BCLK# 3 4
CLK48M C137 *10P RP10 *49.9/FX2
ICS9LP208 ICS954218 3 1 SMBCK CLK_MCH_BCLK 1 2
(16) PCLK_SMB SMBCK (13,19,26)
DEFOULT SETTING CLK_MCH_BCLK# 3 4
pin pin 33MHZ RP16 *49.9/FX2
CLK_XDP 1 2
NO. NO. CLK_XDP# 3 4
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