Service Manuals, User Guides, Schematic Diagrams or docs for : . Various IDX80_la-3291
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download IDX80_la-3291 documenatation <<
Text preview - extract from the document
5 4 3 2 1
Project Name: PecosII
D
(IDX80) D
PCB Serial Number:
LA-3291
PecosII Schematics Document
C C
Intel Merom Dual Core LV1.33G&1.5G
/Yonah Single Core ULV 1.06G&1.2G + Calistoga GM + ICH7-M
2007-01-08
B B
REV: X0.5
A A
Compal Electronics, Inc.(KunShan)
Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom X 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
PecosII-IDX80-LA3291
Monday, January 08, 2007 Sheet 1 of 53
5 4 3 2 1
5 4 3 2 1
DC-DC VCCP&
Block Diagram CPU Thermal Sensor
Clock Generator
ICS9LPRS325AKLF
Fan Control x1
G781F page 6 page 6
CPU_CORE
page 5
page 37 page 46 Merom Dual Core LV
D
/Yonah Single Core ULV D
479 uFCBGA CPU
CRT port
page 6, 7, 8
Docking
CRTpage 36 FSB
HA#[3..31] HD#[0..63] 533/667MHz
CRT CONN.
DDR2 Channel A SO-DIMM x 1
Intel Calistoga GM
page 19
4 BANK page 15
DVI CONN DVI Controller SDVO 1.8V 533/667MHz
USBPORT0
page 18
CH7307 page 18 1466 FCBGA On M/B page 32
Hydis DDR2 Channel B USBPORT 1
LVDS CONN. LVDS port SO-DIMM x 1 On M/B page 32
LCD 12.1" page 17
4 BANK USBPORT 2
page 9, 10, 11, 12, 13, 14 page 16 WWAN
XGA/SXGA+
C C
page 24
USBPORT 3
Finger Printer
page 36
USBPORT 4
LLANO DOCK
DMI x4 1.5V USBPORT 5
page 36
Travel DOCK
page 36
USBPORT 6
LLANO DOCK
PCIE BUS page 36
SIM Mini Card Mini Card USB 2.0 48MHz/480Mb USBPORT 7
card page 24 WWAN 24 WLAN 24
PCIE BUS ICH7-M LLANO DOCK
page 36
page Azalia 3.3V
652 BGA
page
PCIE x1
3.3V 33MHz PCI Bus PATA100
page 20, 21, 22, 23 HDD 1.8"
page 24
B
Azalia Codec B
Gigabit Lan USB 2.0 CardBus STAC9220
LPC Bus 3.3V 33MHz page 30
88E8053 Controller R5C843
page 28 page 27 page 25
Docking AMP & HP &
Port 0
Port 1
Port 2
HP&MIC MIC
page 36 page 31
Transformer PCMCIA Slot
Bluetooth
CardBus
WLAN
& RJ45 page 26 page 35 page 32
page 29
SMSC Embedded Controller TPM
SD Socket
SLB9635TT
page 27
LPC47N217
page 24
page 25
page 26
Docking ENE KB910L
RJ45 express page 33
page 36 card page 26
X Bus ROM DAUGHTER BOARD
A A
SST39VF080
page 34
Digitizer FIR Compal Electronics, Inc.(KunShan)
Title
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom X 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date:
PecosII-IDX80-LA3291
Monday, January 08, 2007 Sheet 2 of 53
5 4 3 2 1
5 4 3 2 1
External PCI Devices Power Management table
DEVICE IDSEL # REQ/GNT # PIRQ +12VALW +1.8V +5VS
+5VALW +3VS
CARD BUS AD20 2 A,B
Signal +3VALW +1.8VS
USB controller AD21 0 E,F,G +3V_LAN +2.5VS
+1.5VS
D +0.9VS D
State
+VCCP
+CPU_CORE
S0 ON ON ON
S1 ON ON ON
S3 ON note1 ON OFF
S5 S4/AC ON note1 OFF OFF
S5 S4/AC don't exist OFF OFF OFF
Note1 : +3V_LAN is ON only with AC power available, otherwise it is OFF.
Symbol Note
Voltage Rails
: means Digital Ground Power Plane Description S0-S1 S3 S5
C VIN Adapter power supply (19V) N/A N/A N/A C
B+ AC or battery power rail for power circuit N/A N/A N/A
: means Analog Ground
+VCC_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.05V power rail for Processor I/O and MCH core power ON OFF OFF
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF
: Question Area Mark.(Wait check) +1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
+1.8V 1.8V power rail for DDRII ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
@: means don't stuff, just reserve +2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
DB@: means jsut stuff when Mini-PCI E Debug card function enable
+3VS 3.3V switched power rail ON OFF OFF
DVI_7307@: means just stuff when use CH7307 controller +5VALW 5V always on power rail ON ON ON*
DVI_1362@: means just stuff when use Sil1362 controller +5VS 5V switched power rail ON OFF OFF
+12VALW 12V always on power rail ON ON ON*
9220@: means just populate when mount 9220 on board; RTCVCC RTC power ON ON ON
depopulate when mount 9228 on board
+3V_LAN 3.3V LAN power rail ON ON* ON*
B
9228@: means just populate when mount 9228 on board; B
depopulate when mount 9220 on board Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
LV@: means just populate when mount Merom/Yonah LV DC CPU on board;
depopulate when mount Yonah ULV SC CPU on board
Buffer@: means just populate when buffer generate V_DDR_MCH_REF;
depopulate when 1.8V divider generate V_DDR_MCH_REF
1.8_divider@: means just populate when 1.8V divider generate V_DDR_MCH_REF;
depopulate when buffer generate V_DDR_MCH_REF
1@: means just populate 0ohm resistors on board;
2@: means just populate MAX9890 & related components on board;
3220@: means populate 0ohm resistors when mount Agilent 3220,unpopulate 0ohm resistors when mount other
A A
Compal Electronics, Inc.(KunShan)
Title
Notes&Revision
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom X 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
PecosII-IDX80-LA3291
Monday, January 08, 2007 Sheet 3 of 53
5 4 3 2 1
5 4 3 2 1
B+
ADAPTER
VS
ACIN SYSON VCCP_ON#
D MAX1902 MAX8743 ISL6269 D
DOCK MAINPWRON SUSP#
DOCK_IN
+3VALW +5VALW +12VALW
+1.8VP
+1.5VSP
+VCCP
SUSP#P LDO SUSP
APL5331 LDO
G965
EC_ON# XC61CN
SUSP
+2.5VSP +1.8VS
A OR B BATTERY
A BATTERY +0.9VSP
SUSP#
C +3VS +VCCP_OK C
+5VS
FSTCHG
MAX1908
A OR B BATTERY
CHARGER IREF
BRIDGE BATTERY
B BATTERY H_DPRSLPVR VID0
H_DPRSTP# VID1
H_PSI# VID2
BATT+
A OR B BATTERY VR_ON VID3
MAX8770
VID4
VGATE
B B
VID5
CLK_ENABLE#
VID6
H_PROCHOT#
FSTCHG
MAX1538
BATSELB_A#
BATTERY SELECTOR
RTC_VREF
VSB
POWER SOURCE +VCC_CORE
BATT+
RTC BATT
G920AT24U
VIN
CHARGER SOURCE
A A
Compal Electronics, Inc.(KunShan)
Title
Power rail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom X 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
PecosII-IDX80-LA3291
Monday, January 08, 2007 Sheet 4 of 53
5 4 3 2 1
5 4 3 2 1
+CK_VDD_MAIN1
L14 +CK_VDD_DP
FSLC FSLB FSLA CPU SRC PCI 1 2
L19
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz FBMA-L11-201209-221LMA30T_0805 1
C384
1
C385
2 2 +3VS 1 2
C386 C387 FBMA-L11-201209-221LMA30T_0805 1 1 1 1
C391 C392 C393 C394
0 0 1 133 100 33.3 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 1 1
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
+CK_VDD_MAIN2
0 1 1 166 100 33.3 L15
R430
+3VS 1 2 1 2 +CK_VDD_REF
FSB Frequency Selet: FBMA-L11-201209-221LMA30T_0805 1 1
C389
1
C390 1_0805_1%
C388
D 1 2 +CK_VDD_48 CLK_CPU_BCLK 2 1 D
Stuff CLK_Ra CLK_Rb CLK_Rc 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R431 R96 @ 49.9_0402_1%
2 2 2 CLK_CPU_BCLK# 2
CPU Driven 2.2_0805_1% 1
R97 @ 49.9_0402_1%
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf CLK_MCH_BCLK 2 1
R98 @ 49.9_0402_1%
CLK_MCH_BCLK# 2 1
Stuff CLK_Rd CLK_Re CLK_Rf R99 @ 49.9_0402_1%
533MHz CLK_CPU_XDP 2 1
No Stuff CLK_Ra CLK_Rb CLK_Rc L4 R100 @ 49.9_0402_1%
CLK_CPU_XDP# 2 1
U46 1 2 +3VS R101 @ 49.9_0402_1%
Stuff CLK_Rd CLK_Rf +CK_VDD_DP FBMA-L11-201209-221LMA30T_0805
667MHz 1 VDDSRC VDDA 7 1 2
No Stuff CLK_Ra CLK_Rb CLK_Rc 49 VDDSRC C415 0.1U_0402_16V4Z
54 VDDSRC GNDA 8
CLK_Re 65 VDDSRC CLK_PCIE_WAN 2 1
+CK_VDD_MAIN1 R102 @ 49.9_0402_1%
25 H_STP_PCI# H_STP_PCI# <22>
PCI_SRC_STOP# CLK_PCIE_WAN# 2 1
30 VDDPCI R103 @ 49.9_0402_1%
36 24 H_STP_CPU# H_STP_CPU# <22> CLK_PCIE_MINI 2 1
VDDPCI CPU_STOP#
R104 @ 49.9_0402_1%
12 VDDCPU CLK_PCIE_MINI# 2 1
+VCCP 11 CK_CPU 1 2 CLK_CPU_BCLK R105 @ 49.9_0402_1%
CPUCLKT1LP CLK_CPU_BCLK <6>
1 2 +CK_VDD_REF 18 VDDREF
◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo