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Global LCD Panel Exchange Center www.panelook.com
Model Name: T315XW06 V7
Issue Date : 2010/08/20
( )Preliminary Specifications
( )Final Specifications
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Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORMS
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT SPECIFICATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DEFINITION OF LABEL
8-2 PACKING METHODS
8-3 PALLET AND SHIPMENT INFORMATION
9 PRECAUTIONS
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECT FILM
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Record of Revision
Version Date Page Description
0.0 2010/08/20 First release
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1. General Description
This specification applies to the 31.5 inch Color TFT-LCD Module T315XW06 V7. This LCD module has a TFT
active matrix type liquid crystal panel 1,366 x 768 pixels, and diagonal size of 31.5 inch. This module supports
1,366 x 768 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
The T315XW06 V7 has been designed to apply the 8-bit 1 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important.
z General Information
Items Specification Unit Note
Active Screen Size 31.5 inch
Display Area 697.685 (H) x 392.256(V) mm
Outline Dimension 735.4 (H) x 433.8 (V) x 10.8 (D) mm
Driver Element a-Si TFT active matrix
Display Colors 8 bit, 16.7M color
Number of Pixels 1,366 x 768 pixel
Pixel Pitch 0.51075 mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment Anti-Glare, 3H Haze=2%
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2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
o
Storage Temperature TST -20 +60 [ C] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
o
Panel Surface Temperature PST -- 65 [ C] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
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3. Electrical Specification
The T315XW06 V7 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal. The second input for BLU is to power inverter.
3-1 Electrical Characteristics
3.1.1: DC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage (for input power=12V) VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD -- 0.26 0.33 A 1
Inrush Current IRUSH -- -- 3 A 2
Input Differential Voltage VID 200 400 600 mVDC 3
LVDS Differential Input High Threshold Voltage VTH +100 -- +300 mVDC 3
Interface
Differential Input Low Threshold Voltage VTL -300 -- -100 mVDC 3
Input Common Mode Voltage VICM 1.1 1.25 1.4 VDC 3
VIH
CMOS Input High Threshold Voltage 2.7 -- 3.3 VDC 5
(High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.6 VDC 5
(Low)
Backlight Power Consumption PBL 38.4 40.66 Watt
3.1.2: AC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
Receiver Clock : Spread Spectrum Fclk Fclk
Fclk_ss -- MHz 7
Modulation range -3% +3%
Receiver Clock : Spread Spectrum
LVDS Fss 30 -- 200 KHz 7
Modulation frequency
Interface
Receiver Data Input Margin
Fclk = 85 MHz tRMG -0.4 -- 0.4 ns 8
Fclk = 65 MHz -0.5 -- 0.5
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Note :
1. Test Condition:
(1) VDD = 12.0V
(2) Fv = 60 Hz
(3) Fclk= Max freq.
(4) Temperature = 25
(5) Typ. Input current : White Pattern
Max. Input current: Heavy loading pattern defined by AUO
2. Measurement condition : Rising time = 400us
9''
*1'
s
3. VICM = 1.25V
LVDS -
V IC M V TH
|V ID |
V TL
LVDS +
GND
|V ID |
0V
|V ID |
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4. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM.
5. Input Channel Pair Skew Margin
Note: x = 0, 1, 2, 3, 4
6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
)66
)FONB
)FONBVV PD[
)FON
)FONB
)FONBVV PLQ
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T315XW06 V7 Product Specification
Rev. 0.0
7. Receiver Data Input Margin
Rating
Parameter Symbol Unit Note
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz T=1/Fclk
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG| 2T/7 2T/7+|tRMG| ns
Input Data Position3 tRIP5 3T/7-|tRMG| 3T/7 3T/7+|tRMG| ns
Input Data Position4 tRIP4 4T/7-|tRMG| 4T/7 4T/7+|tRMG| ns
Input Data Position5 tRIP3 5T/7-|tRMG| 5T/7 5T/7+|tRMG| ns
Input Data Position6 tRIP2 6T/7-|tRMG| 6T/7 6T/7+|tRMG| ns
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