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                                                                                Document Version : 1
                                                                                   Date : 2008/04/01




                                                                       Product Specifications

                                                      37" HDTV Color TFT-LCD Module
                                                          Model Name: T370HW02. VC




                                                              () Preliminary Specifications
                                                                   (*) Final Specifications




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                                                        Contents

            No

                     COVER


                     CONTENTS


                     RECORD OF REVISIONS


           1         GENERAL DESCRIPTION


           2         ABSOLUTE MAXIMUM RATINGS


           3         ELECTRICAL SPECIFICATIONS


               3-1   ELECTRICAL CHARACTREISTICS


               3-2   INTERFACE CONNECTIONS


               3-3   SIGNAL TIMING SPECIFICATIONS


               3-4   SIGNAL TIMING WAVEFORMS


               3-5   COLOR INPUT DATA REFERNECE


               3-6   POWER SEQUENCE


               3-7   Backlight Unit Specification


            4        OPTICAL SPECIFICATIONS


            5        MECHANICAL CHARACTERISTICS


            6        RELIABLITY


            7        INTERNATIONAL STANDARDS


            8        PACKING


            9        PRECAUTIONS




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                                                    Record of Revision
               Version Date      No           Old Description           New Description   Remark
                  0    2008/12        First issue

                  1    2008/4                                    Modify drawing




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               1. General Description
               This specification applies to the 37.0 inch Color TFT-LCD Module T370HW02 VC. This
               LCD module has a TFT active matrix type liquid crystal panel 1920*1080 pixels, and
               diagonal size of 37.0 inch. This module supports 1920*1080 HDTV mode (Non-interlace).
               Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in
               vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit
               gray scale signal for each dot.
               The T370HW02 VC has been designed to apply the 8-bit 2 channel LVDS interface method.
               It is intended to support displays where high brightness, wide viewing angle, high color
               saturation, and high color depth are very important.
               The T370HW02 VC model is RoHS verified which can be distinguished on panel label.




               * General Information
               Items                        Specification                 Unit          Note
               Active Screen Size           37.01                         inch
               Display Area                 819.36 (H) x 460.89(V)        mm
               Outline Dimension            877(H) x 514.6(V) x 47.6(D)   mm            LIPS type
               Driver Element               a-Si TFT active matrix
               Display Colors               8 bit, 16.7M                  Colors
               Number of Pixels             1920 x 1080                   Pixel
               Pixel Pitch                  0.42675(H) x 0.42675(W)       mm
               Pixel Arrangement            RGB vertical stripe
               Display Operation Mode       Normally Black
               Surface Treatment            Anti-Glare, 3H                              Haze = 11




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               2. Absolute Maximum Ratings
               The following are maximum values which, if exceeded, may cause permanent damage to the
               unit.

                                 Item                  Symbol      Min               Max        Unit        Conditions
                Logic/LCD Drive Voltage                  Vcc        -0.3              14        [Volt]        Note 1
                Input Voltage of Signal                  Vin        -0.3             3.6        [Volt]        Note 1
                BLU Input Voltage                      VDDB         -0.3             28         [Volt]        Note 1
                BLU Brightness Control Voltage          Vdim        -0.3             7.0        [Volt]        Note 1
                                                                                                 o
                Operating Temperature                   TOP          0               +50         [ C]         Note 2
                Operating Humidity                      HOP         10               90         [%RH]         Note 2
                Storage Temperature                     TST         -20              +60         [oC]         Note 2
                Storage Humidity                        HST         10               90         [%RH]         Note 2
                                                                                                 o
                Panel Surface Temperature                PST                         65          [ C]         Note 3

               Note 1: Duration:50 msec.
               Note 2 : Maximum Wet-Bulb should be 39       and No condensation.
               The relative humidity must not exceed 90% non-condensing at temperatures of 40     or less. At temperatures
               greater than 40   , the wet bulb temperature must not exceed 39   .
               Note 3: Surface temperature is measured at 50    Dry condition




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               3. Electrical Specification
               The T370HW02 VC requires two power inputs. One is employed to power the LCD electronics and to drive the
               TFT array and liquid crystal. The second input power for the BLU, is to power inverter. (INV)

               3-1 Electrical Characteristics
                                     Parameter                                              Values       Unit    Notes
                                                                               Min     Typ      Max




                   LCD:
                     Power Supply Input Voltage                       Vcc      10.8    12       13.2     Vdc      1
                     Power Supply Input Current                       Icc       -       1        1.2      A       2
                     Power Consumption                                Pc        -      12       14.4     Watt     2
                     Inrush Current                                  IRUSH      -       -            4   Apeak    3
                   LVDS          Differential Input High Threshold   VTH                        100       mV      4
                   Interface     Voltage

                                 Differential Input Low Threshold    VTL       -100                       mV      4
                                 Voltage

                                 Common Input Voltage                VCIM      1.10    1.25     1.40      V       4

                    CMOS Input High Threshold Voltage                 VIH      2.4               3.3     Vdc
                   Interface                                         (High)
                                 Input Low Threshold Voltage          VIL       0                0.9     Vdc
                                                                     (Low)
                   Life Time                                                  50,000                     Hours


                   Note :
                            1.     The ripple voltage should be controlled under 10% of VCC
                            2.     Vcc=12.0V,     f v = 60Hz, fCLK=81.5Mhz , 25 , Test Pattern : White Pattern
                            3.     Measurement condition :




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                          4.   VCIM = 1.2V


                                                                                                VTH
                                      VCIM
                                                                                                 VIL




                                         0V

                          5.   The performance of the Lamp in LCD panel, for example life time or brightness, is extremely
                               influenced by the characteristics of the DC-AC Inverter. So all the parameters of an inverter
                               should be carefully designed as not to produce too much leakage current from high-voltage
                               output of the inverter. When you design or order the inverter, please make sure unwanted
                               lighting caused by the mismatch of the lamp and the inverter (no lighting, flicker, etc) never
                               occurs. After confirmation, the LCD panel should be operated in the same condition as
                               installed in your instrument.
                          6.   Do not attach a conducting tape to lamp connecting wire. If the lamp wire attach to conducting
                               tape, TFT-LCD Module have a low luminance and the inverter has abnormal action because
                               leakage current occurs between lamp wire and conducting tape.
                   7.   The relative humidity must not exceed 80% non-condensing at temperatures of 40              or less. At
                        temperatures greater than 40   , the wet bulb temperature must not exceed 39   . When operate at low
                        temperatures, the brightness of CCFL will drop and the life time of CCFL will be reduced.




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               3-2 Interface Connections
               LCD connector (CN3): JAE FI-RE51S-HF
                   Pin No    Symbol                       Description                    Note
                      1       VDD        Operating Voltage Supply, +12V DC Regulated
                      2       VDD      Operating Voltage Supply, +12V DC Regulated
                      3       VDD      Operating Voltage Supply, +12V DC Regulated
                      4       VDD      Operating Voltage Supply, +12V DC Regulated
                      5       VDD      Operating Voltage Supply, +12V DC Regulated      Power
                      6       GND                         Ground
                      7       GND                         Ground
                      8       GND                         Ground
                      9       GND                         Ground
                     10      RO_0-             LVDS Channel Odd, Signal 0-
                     11      RO_0+             LVDS Channel Odd, Signal 0+
                     12      RO_1-             LVDS Channel Odd, Signal 1-
                     13      RO_1+             LVDS Channel Odd, Signal 1+
                     14      RO_2-             LVDS Channel Odd, Signal 2-
                     15      RO_2+             LVDS Channel Odd, Signal 2+
                     16       GND                         Ground                        LVDS
                     17     RO_CLK-              LVDS Channel Odd, Clock -             Channel
                     18     RO_CLK+             LVDS Channel Odd, Clock +                Odd
                     19       GND                         Ground
                     20      RO_3-             LVDS Channel Odd, Signal 3-
                     21      RO_3+             LVDS Channel Odd, Signal 3+
                     22       NC            No Connect (AUO Internal Use Only)
                     23       NC            No Connect (AUO Internal Use Only)
                     24       GND                         Ground
                     25      RE_0-             LVDS Channel Even, Signal 0-
                     26      RE_0+            LVDS Channel Even, Signal 0+
                     27      RE_1-             LVDS Channel Even, Signal 1-
                     28      RE_1+            LVDS Channel Even, Signal 1+
                     29      RE_2-             LVDS Channel Even, Signal 2-
                     30      RE_2+            LVDS Channel Even, Signal 2+
                     31       GND                         Ground                        LVDS
                     32     RE_CLK-             LVDS Channel Even, Clock -             Channel
                     33     RE_CLK+             LVDS Channel Even, Clock +              Even
                     34       GND                         Ground
                     35      RE_3-             LVDS Channel Even, Signal 3-
                     36      RE_3+            LVDS Channel Even, Signal 3+
                     37       NC            No Connect (AUO Internal Use Only)
                     38       NC            No Connect (AUO Internal Use Only)
                     39       GND                         Ground
                     40       SCL                  EEPROM Serial Clock
                     41       NC            No Connect (AUO Internal Use Only)
                     42       NC            No Connect (AUO Internal Use Only)
                                                 EEPROM Write Protection               Default:
                     43        WP
                                     High(3.3V) for Writable, Low(GND) for Protection Protection
                     44        SDA                 EEPROM Serial Data
                     45     LVDS_SEL   Open/High(3.3V) for NS, Low(GND) for JEIDA     Default: NS
                     46        NC           No Connect (AUO Internal Use Only)
                     47        NC           No Connect (AUO Internal Use Only)
                     48        NC           No Connect (AUO Internal Use Only)
                     49        NC           No Connect (AUO Internal Use Only)
                     50        NC           No Connect (AUO Internal Use Only)
                     51       AGING           No Connect (AUO Aging Only)
                   Note:
                   1. All GND (ground) pins should be connected together and should also be connected to the LCD's metal
                       frame. All Vcc (power input) pins should be connected together.
                   2. For Pin 10, 27 and 28, panel will not damage if negligently connect these pins to high or low




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                LVDS Option = Hi (3.3V) or Open = NS




                LVDS Option = Lo (GND) = JEIDA




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               3-3 Signal Timing Specifications
               This is the signal timing required at the input of the User connector. All of the interface signal timing should be
               satisfied with the following specifications for it's proper operation.

               * Timing Table
               DE only Mode
                     Signal               Item             Symbol           Min          Type           Max           Unit
                                         Period          Tv                1090          1125           1480           Th
                    Vertical
                                         Active          Tdisp (v)                        1080                         Th
                    Section
                                        Blanking         Tblk (v)            10            45            400           Th
                                         Period          Th                1030          1100           1325          Tclk
                  Horizontal
                                         Active          Tdisp (h)                         960                        Tclk
                   Section
                                        Blanking         Tblk (h)            70           140            340          Tclk
                 LVDS Clock           Frequency          1/Tclk              50          74.25           82          MHz
                   Vertical
                                      Frequency          Freq                47            60            63            Hz
                  Frequency
                  Horizontal
                                      Frequency          Freq                60          67.5            73           KHz
                  Frequency


               Notes:
               1.) Display position is specific by the rise of DE signal only.
               Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on
               the left edge of the screen.
               Vertical display position is specified by the rise of DE after a "Low" level period equivalent to eight times of
               horizontal period. The 1st data corresponding to one horizontal line after the rise the of 1st DE is displayed at the
               top line of screen.
               3.) If a period of DEB "High" is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays
               black.
               4.) The display position does not fit to the screen if a period of DE "High" and the effective data period do not
               synchronize with each other.




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                                                                                                                                                  Tv
                                                                                                                    Tblk(v)                                                    Tdisp(v)
                                                                                                                                      Th
                                                                             DE
                                                                        RGB
                                                                                           N                  Invalid Data              1                2               3                   4                         N                  Invalid Data
                                                                        Data
                                                                                          Line                                        Line             Line             Line               Line                       Line
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                                                                       CLK
                                                                                                                                                                         Th
                                                                                                          Tclk
                                                                                                                                                                        Tdisp(h)                                                Tblk(h)
                                      3-4 Signal Timing Waveforms




                                                                        DE
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                                                                    RGB Data      Pixel   Pixel   Pixel   Pixel                        Pixel   Pixel    Pixel   Pixel    Pixel     Pixel          Pixel   Pixel   Pixel                                  Pixel   Pixel
                                                                                                                       Invalid Data                                                                                          Invalid Data
                                                                      (odd)       M-7     M-5     M-3     M-1                            1       3        5       7        9        11            M-5     M-3     M-1                                      1       3
                                                                    RGB Data      Pixel   Pixel   Pixel   Pixel                        Pixel   Pixel    Pixel   Pixel    Pixel     Pixel          Pixel   Pixel   Pixel                                  Pixel   Pixel
                                                                                                                       Invalid Data                                                                                          Invalid Data
                                                                     (even)       M-6     M-4     M-2      M                             2       4        6       8       10        12            M-4     M-2      M                                       2       4
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                 3-5 Color Input Data Reference
                 The brightness of each primary color (red, green and blue) is based on the 8 bit gray scale data input for the
                 color; the higher the binary input, the brighter the color. The table below provides a reference for color versus
                 data input.
                                                     COLOR        DATA REFERENCE


                                                                               Input Color Data
           Color                                 RED                                GREEN                               BLUE
                                   MSB                           LSB MSB                              LSB MSB                           LSB
                                   R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
                    Black           0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   0   0    0   0   0   0   0    0
                    Red(255)        1    1   1   1   1   1   1    1   0    0    0   0   0   0     0    0   0   0    0   0   0   0   0    0
                    Green(255)      0    0   0   0   0   0   0    0   1    1    1   1   1   1     1    1   0    0   0   0   0   0   0    0
           Basic    Blue(255)       0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   1   1    1   1   1   1   1    1
           Color    Cyan            0    0   0   0   0   0   0    0   1    1    1   1   1   1     1    1   1   1    1   1   1   1   1    1
                    Magenta         1    1   1   1   1   1   1    1   0    0    0   0   0   0     0    0   1    1   1   1   1   1   1    1
                    Yellow          1    1   1   1   1   1   1    1   1    1    1   1   1   1     1    1   0   0    0   0   0   0   0    0
                    White           1    1   1   1   1   1   1    1   1    1    1   1   1   1     1    1   1   1    1   1   1   1   1    1
                    RED(000)        0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   0   0    0   0   0   0   0    0
                    RED(001)        0    0   0   0   0   0   0    1   0    0    0   0   0   0     0    0   0   0    0   0   0   0   0    0
           RED          ----
                    RED(254)        1    1   1   1   1   1   1    0   0    0    0   0   0   0     0    0   0   0    0   0   0   0   0    0
                    RED(255)        1    1   1   1   1   1   1    1   0    0    0   0   0   0     0    0   0   0    0   0   0   0   0    0
                    GREEN(000) 0         0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   0    0   0   0   0   0   0    0
                    GREEN(001) 0         0   0   0   0   0   0    0   0    0    0   0   0   0     0    1   0    0   0   0   0   0   0    0
           GREEN        ----
                    GREEN(254) 0         0   0   0   0   0   0    0   1    1    1   1   1   1     1    0   0    0   0   0   0   0   0    0
                    GREEN(255) 0         0   0   0   0   0   0    0   1    1    1   1   1   1     1    1   0    0   0   0   0   0   0    0
                    BLUE(000)       0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   0    0   0   0   0   0   0    0
                    BLUE(001)       0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   0    0   0   0   0   0   0    1
           BLUE         -------
                    BLUE(254)       0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   1    1   1   1   1   1   1    0
                    BLUE(255)       0    0   0   0   0   0   0    0   0    0    0   0   0   0     0    0   1    1   1   1   1   1   1    1




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               3-6 Power Sequence for LCD Module
                3.6.1 Power Sequence for LCD




                                                               Value
                 Parameter                                                                             Units
                                         Min.                    Typ.                 Max.
                       T1                 0.4                     ---                      30           ms
                       T2                 0.1                     ---                      50           ms
                       T3                 300                     ---                      ---          ms
                       T4                 10                      ---                      ---          ms
                       T5                 0.1                     ---                      50           ms
                       T6                 ---                     ---                  300              ms
                       T7                 500                     ---                      ---          ms

               Note:
                  The timing controller will not be damaged in case of TV set AC input power suddenly shut down.
                  Once power reset, it should follow power sequence as spec. definition.


               (1) Apply the lamp voltage within the LCD operation range. When the back-light turns on before the LCD
                   operation or the LCD turns off before the back-light turns off, the display may momentarily become
                   abnormal screen.




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               3-7 Backlight Unit Specification
               3.7.1 Electrical specification
                                  Description                 Min       Typ     Max      Unit                Condition/Note

                                                                                                 1. Dimming range is set 100%
                                                                                                 2. Base on lamp specification, for each
                1 Operating Voltage                  Vo       846       940     1034     Vrms       lamp need to be applied at least
                                                                                                    minimum operating voltage to ensure
                                                                                                    each lamp can be normally worked!

                                                                                                 1. Dimming range is set 100%
                                                                                                 2. Base on lamp specification, for each
                2 Operating Current                  Io       9.5        10     11.5     mArms      lamp need to be applied at least
                                                                                                    minimum operating current to ensure
                                                                                                    each lamp can be normally worked!

                                                                                                 1. Dimming range is set 100%.
                                                                                                 2. In order to get typical light out, the
                                                                                                    backlight need to be applied typical
                3 BL Total Power Dissipation        PBL        85        90    103.5     Watt       power.
                                                                                                 3. Input power of JIG BD is about 90 W
                                                                                                    (typ) by AUO measure!

                                       At 0                  1500      1700         -            1. Base on lamp specification, to ensure
                                                                                                    each lamp can be normally ignited,
                4 Striking Voltage                 Vstrike                               Vrms       need to apply at least minimum
                                       At                    1250      1450         -               striking voltage to each lamp

                                                                                                 1. To ensure each lamp can be normally
                                                                                                    ignited, each lamp need to be applied
                5 Striking Time                      Ts      1000         -     1500     msec       at least minimum striking voltage
                                                                                                    during minimum striking time.

                                                                                                 1. Operating frequency is set by
                                                                                                    customer.
                6 Operating Frequency                fo        42        44         45    kHz    2. Need to double confirm display
                                                                                                    quality.(*)


                                                                                                 1. PWM frequency is set by customer.
                7 PWM Operating Frequency          F_PWM      140       180     240       Hz     2. Need to double confirm display
                                                                                                    quality.(*)


                                                                                                 Note 1. Dimming range
                8 PWM Dimming Duty Ratio           D_PWM       20         -     100       %      Note 2.
                                                                                                 Note 3. Duty ratio definition.


                9 Lamp Type                                         Straight type
                10 Number of Lamps                                       10               pcs
                                                                                     Ta=25 5    , Turn on for 45minutes
               (*) The operating frequency of lamp may produce interference with horizontal frequency from display,
               and may cause line noise on the display. In order to avoid interference, the operating frequency should
               be separated from horizontal frequency.

               Note 1:
               Dimming range
                         Control              0%                                                               100%
                          range

                           PWM                     20%                                                         100%
                          Dimming


                                        PWM Dimming : include Internal and External PWM Dimming




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               Note 2:
               When PWM dimming ration is operated less than recommend value, backlight need to be double
               confirmed display quality. LIPS need to be double confirmed feedback signal and all protection
               function!

               Note 3:
               Duty ratio definition.




               3.7.2 Lamp specification
                                  Description              Min        Typ       Max         Unit               Note
                 1    Lamp voltage              Vlamp      846         940      1034        Vrms        At Ilamp=10.0mA
                 2    Lamp current              Ilamp       -         10.0        -        mArms
                 3    Lamp frequency            flamp      35           -        80          kHz
                                                At 2        -           -       1250        Vrms
                 4    Striking voltage
                                                At          -           -       1500        Vrms
                      Delayed discharge
                 5                              Tdelay      -           -       1000        msec
                      time
                 6    Life time                            50K          -         -           hr
                 7    Unsymmetrical ratio                   -           -       10%           -
                                                                                                     Note 1.
                 8 Crest factor (C.F)                    2 - 10%           2   2 + 10%        -
               The above characteristics are measured under the conditions:
               Ambient temperature: 25



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