Service Manuals, User Guides, Schematic Diagrams or docs for : . Various LCD Panels Panel_AUO_T390HVN01-0_0_[DS]
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Global LCD Panel Exchange Center www.panelook.com
Model Name: T390HVN01.0
Issue Date : 2011/12/01
( )Preliminary Specifications
( )Final Specifications
Customer Signature Date AUO Date
Approved By Approval By PM Director
_________________________________ ____________________________________
Note Reviewed By RD Director
____________________________________
Reviewed By Project Leader
____________________________________
Prepared By PM
____________________________________
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Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT POWER SPECIFICATION
4 OPTICAL SPECIFICATION
5 OPEN CELL DRAWING
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
8 PACKING
8-1 OPEN CELL SHIPPING LABEL
8-2 PACKING PROCESS
8-3 PALLET AND SHIPMENT INFORMATION
9 PRECAUTION
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECT FILM
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Record of Revision
Version Date Page Description
0.0 2011/12/09 First release
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1. General Description
This specification applies to the 38.5 inch Color TFT-LCD Module T390HVN01.0. This LCD module has a TFT
active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 38.5 inch. This module supports
1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
The T390HVN01.0 has been designed to apply the 8-bit 2 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important.
General Information
Items Specification Unit Note
Active Screen Size 38.5 inch
Display Area 853.92 (H) x 480.33 (V) mm
Outline Dimension 898.92 (H) x 525.33 (V) x 55.5 (D) mm
Driver Element a-Si TFT active matrix
Display Colors 8 bit Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.44475 (H) x 0.44475 (W) mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment Anti-Glare, 3H Haze=2%
Rotate Function Unachievable Note 1
Display Orientation Signal input with "A" Note 2
Note 1: Rotate Function refers to LCD display could be able to rotate.
Note 2: LCD display as below illustrated when signal input with "A".
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2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 14 VDC Note 1
Input Voltage of Signal Vin -0.3 4 VDC Note 1
T-B/B Input Voltage VBB - 500 Vp-p Note 2
Supply control Voltage Vcc -0.3 15 VDC Note 2
Note 1: Duration: 50 msec.
Note 2: Duration: 2 sec.
3. Electrical Specification
The T390HVN01.0 module requires power input which is employed to power the LCD electronics and to drive the
TFT array and liquid crystal.
3-1 Electrical Characteristics
3-1.1: DC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD -- 0.8 1.3 A 1
Inrush Current IRUSH -- -- 4 A 2
Permissible Ripple of Power Supply Input Voltage
VRP -- -- VDD * 5% mVpk-pk 3
Input Differential Voltage VID 200 400 600 mVDC 4
LVDS Differential Input High Threshold Voltage VTH +100 -- +300 mVDC 4
Interface
Differential Input Low Threshold Voltage VTL -300 -- -100 mVDC 4
Input Common Mode Voltage VICM 1.1 1.25 1.4 VDC 4
VIH
CMOS Input High Threshold Voltage 2.7 -- 3.3 VDC 5
(High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.6 VDC 5
(Low)
Backlight Power Consumption PBL 105 117 129 Watt
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3-1.2: AC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
Receiver Clock : Spread Spectrum Fclk Fclk
Fclk_ss -- MHz 6
Modulation range -3% +3%
Receiver Clock : Spread Spectrum
LVDS Fss 30 -- 200 KHz 6
Modulation frequency
Interface
Receiver Data Input Margin
Fclk = 85 MHz tRMG -0.4 -- 0.4 ns 7
Fclk = 65 MHz -0.5 -- 0.5
Note :
1. Test Condition:
(1) VDD = 12.0V
(2) Fv = Type Timing, 60Hz, 120Hz or Other
(3) Fclk= Max freq.
(4) Temperature = 25
(5) Typ. Input current : White Pattern
Max. Input current: Heavy loading pattern defined by AUO
>> refer to "Section:3.3 Signal Timing Specification, Typical timing"
2. Measurement condition : Rising time = 400us
9''
*1'
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