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Product Description: T400HW02 TFT-LCD PANEL with RoHS guarantee
AUO Model Name: T400HW02 V5
Customer Part No/Project Name:
Customer Signature Date AUO Date
Approved By: PM Director / Frank Hsu
--------------------------------------------
Reviewed By: RD Director / Hong Jye Hong
--------------------------------------------
Reviewed By: Project Leader /Bruce Liu
--------------------------------------------
Prepared By: PM /Cynthia Hung
---------------------------------------------
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Document Version: 0.0
Date:2008/09/30
Product Specifications
40" Full HD Color TFT-LCD Module
Model Name: T400HW02 V5
(*) Preliminary Specifications
() Final Specifications
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Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT CONNECTOR PIN CONFIGURATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 Safety
7-2 EMC
8 PACKING
9 PRECAUTION
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Record of Revision
Version Data No Old Description New Decription Remark
0.0 2008/09/30 First release N/A
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1. General Description
This specification applies to the 40.0 inch Color TFT-LCD Module T400HW02 V5. This LCD
module has a TFT active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 40.0
inch. This module supports 1,920x1,080 mode. Each pixel is divided into Red, Green and Blue
sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel
color is determined with a 10-bit gray scale signal for each dot.
The T400HW02 V5 has been designed to apply the 10-bit 2 channel LVDS interface method. It is
intended to support displays where high brightness, wide viewing angle, high color saturation, and
high color depth are very important.
* General Information
Items Specification Unit Note
Active Screen Size 40.00 inch
Display Area 885.6(H) x 498.15(V) mm
Outline Dimension 952.0(H) x 551.0 (V) x 49.6(D) mm With T-con cover
Driver Element a-Si TFT active matrix
Display Colors 10 bit, 1073.7M Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.46125 (H) x 0.46125(W) mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Super Clear
Surface Treatment
(Anti-reflection coating)
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2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the
unit
Item Symbol Min Max Unit Condition
s
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 3.6 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
o
Storage Temperature TST -20 +60 [ C] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
Panel Surface Temperature PST 65 [ oC] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At
temperatures greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
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3. Electrical Specification
The T400HW02 V5 requires two power inputs. One is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second input, which powers the CCFL, is typically
generated by an integrate power (I/P) system.
3.1 Electrical Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage V DD 10.8 12 13.2 V DC 1
Power Supply Input Current I DD -- 1.14 1.25 A 2
Power Consumption PC -- 13.68 15.0 Watt 2
Inrush Current I RUSH -- -- 4.5 A 3
Differential Input High Threshold
VTH -- -- +100 mVDC 4
Voltage
LVDS Differential Input Low Threshold
VTL -100 -- -- mVDC 4
Interface Voltage
Input Common Mode Voltage V ICM 0.6 1.2 1.8 V DC 4
VIH
Input High Threshold Voltage 2.4 -- 3.3 VDC
CMOS (High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.7 VDC
(Low)
Life Time 50000 -- Hours
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Note :
1. The ripple voltage should be controlled under 10% of V CC
2. Vcc=12.0V, f v = 60Hz, fCLK=81.5Mhz , 25 , Test Pattern : White Pattern
3. Measurement condition :
Vdd
0.9 Vdd
0.1 Vdd
GND
400s
4. VCIM = 1.2V
VTH
VCIM
VTL
0V
5. The performance of the Lamp in LCD panel, for example life time or brightness, is extremely
influenced by the characteristics of balanced board and I/P board. All the parameters should
be carefully designed as not to produce too much leakage current from high-voltage output.
While you design or order the balance board, please make sure unwanted lighting caused by
the mismatch of the lamp and the balanced board (no lighting, flicker, etc) never occurs. After
confirmation, the LCD panel should be operated in the same condition as installed in your
instrument
6. Do not attach a conducting tape to lamp connecting wire. If the lamp wire attach to conducting
tape, TFT-LCD Module have a low luminance and the inverter has abnormal action because
leakage current occurs between lamp wire and conducting tape.
7. The relative humidity must not exceed 80% non-condensing at temperatures of 40 or less.
At temperatures greater than 40 , the wet bulb temperature must not exceed 39 . When
operate at low temperatures, the brightness of CCFL will drop and the life time of CCFL will be
reduced.
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3.2 Interface Connections
LCD connector: FI-RE51S-HF (JAE)
Mating connector: FI-RE51S-HL (JAE)
PIN # Signal Name Description
1 VDD Operating Voltage Supply, +12V DC Regulated
2 VDD Operating Voltage Supply, +12V DC Regulated
3 VDD Operating Voltage Supply, +12V DC Regulated
4 VDD Operating Voltage Supply, +12V DC Regulated
5 VDD Operating Voltage Supply, +12V DC Regulated
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 RO_0- LVDS Channel Odd, Signal 0-
11 RO_0+ LVDS Channel Odd, Signal 0+
12 RO_1- LVDS Channel Odd, Signal 1-
13 RO_1+ LVDS Channel Odd, Signal 1+
14 RO_2- LVDS Channel Odd, Signal 2-
15 RO_2+ LVDS Channel Odd, Signal 2+
16 GND Ground
17 RO_CLK- LVDS Channel Odd, Clock -
18 RO_CLK+ LVDS Channel Odd, Clock +
19 GND Ground
20 RO_3- LVDS Channel Odd, Signal 3-
21 RO_3+ LVDS Channel Odd, Signal 3+
22 NC No Connect (Reserved for 10-bit)
23 NC No Connect (Reserved for 10-bit)
24 GND Ground
25 RE_0- LVDS Channel Even, Signal 0-
26 RE_0+ LVDS Channel Even, Signal 0+
27 RE_1- LVDS Channel Even, Signal 1-
28 RE_1+ LVDS Channel Even, Signal 1+
29 RE_2- LVDS Channel Even, Signal 2-
30 RE_2+ LVDS Channel Even, Signal 2+
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31 GND Ground
32 RE_CLK- LVDS Channel Even, Clock -
33 RE_CLK+ LVDS Channel Even, Clock +
34 GND Ground
35 RE_3- LVDS Channel Even, Signal 3-
36 RE_3+ LVDS Channel Even, Signal 3+
37 NC No Connect (Reserved for 10-bit)
38 NC No Connect (Reserved for 10-bit)
39 GND Ground
40 SCL_TCON Please leave it open
41 SDA_TCON Please leave it open
42 NC Please leave it open
B_INT(same as WP);EEPROM Write Protection
43 B_INT
High(3.3V) for Writable, Low(GND) for Protection
44 Hsync_OUT H-Sync Output for Inverter/IPB
45 LVDS_SEL Open/High(3.3V) for NS, Low(GND) for JEIDA
46 SCL_FRC EEPROM Serial Clock for FRC
47 Reset_FRC Reset for FRC Chip
48 SDA_FRC EEPROM Serial Data for FRC
49 PVCC_SW Panel VCC Sequence Control
Detection Pin to Check if System Board Connected
50 SYS_DET
(GND if connected)
51 NC Please leave it open
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LVDS Option = High/Open NS
Previous Cycle Current Cycle Next Cycle
Clock
RIN0+
R1 R0 G0 R5 R4 R3 R2 R1 R0 G0
RIN0-
RIN1+
G2 G1 B1 B0 G5 G4 G3 G2 G1 B1
RIN1-
RIN2+
B3 B2 DE NA NA B5 B4 B4 B2 DE
RIN2-
RIN3+
R7 R6 NA B7 B6 G7 G6 R7 R6 NA
RIN3-
LVDS Option = Low JEIDA
Previous Cycle Current Cycle Next Cycle
Clock
RIN0+
R3 R2 G2 R7 R6 R5 R4 R3 R2 G2
RIN0-
RIN1+ G4 G3 B3 B2 G6 G6 G5 G4 G3 B3
RIN1- G7
RIN2+
B5 B4 DE NA NA B7 B6 B5 B4 DE
RIN2-
RIN3+
R1 R0 NA B1 B0 G1 G0 R1 R0 NA
RIN3-
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3.3 Signal Timing Specification
This is the signal timing required at the input of the user connector. All of the interface signal timing
should be satisfied with the following specifications for its proper operation.
Timing Table (DE only Mode)
For 60Hz
Signal Item Symbol Min. Typ. Max Unit
Period TV 1125 TH
Vertical Section Active TDISP (V) 1080 TH
Blanking T BLK (V) 45 TH
Period TH 1100 TCLK
Horizontal Section Active TDISP (H) 960 TCLK
Blanking T BLK (H) 140 TCLK
Clock Frequency 1/T CLK 74.25 MHz
Vertical Frequency Frequency FV 60 Hz
Horizontal Frequency Frequency FH 67.5 KHz
Notes:
1.) Display position is specific by the rise of DE signal only.
st st
Horizontal display position is specified by the rising edge of 1 DCLK after the rise of 1 DE, is
displayed on the left edge of the screen.
Vertical display position is specified by the rise of DE after a "Low" level period equivalent to eight
times of horizontal period. The 1 st data corresponding to one horizontal line after the rise the of 1 st DE
is displayed at the top line of screen.
3.) If a period of DE "High" is less than 1366 DCLK or less than 768 lines, the rest of the screen
displays black.
4.) The display position does not fit to the screen if a period of DE "High" and the effective data period
do not synchronize with each other.
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3.4 Signal Timing Waveforms
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3.5 Color Input Data Reference
The brightness of each primary color (red, green and blue) is based on the 8 bit gray scale data input for
the color; the higher the binary input, the brighter the color. The table below provides a reference for color
versus data input.
COLOR DATA REFERENCE
Input Color Data
RED GREEN BLUE
Color MSB LSB MSB MSB LSB
LSB
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Basic
Blue(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Color
Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RED(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(001) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED ----
RED(1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
GREEN ----
GREEN(1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
GREEN(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
BLUE(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLUE(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
BLUE -------
BLUE(1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0
BLUE(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
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3.6 Power Sequence
Values
Parameter Unit
Min. Typ. Max.
t1 0.4 -- 30 ms
t2 0.1 -- 50 ms
t3 2300 -- -- ms
t4 10 -- -- ms
t5 0.1 -- 50 ms
t6 -- -- 300 ms
t7 500 -- -- ms
Note:
The timing controller will not be damaged in case of TV set AC input power suddenly shut down.
Once power reset, it should follow power sequence as spec. definition.
(1) Apply the lamp voltage within the LCD operation range. When the back-light turns on before the LCD
operation or the LCD turns off before the back-light turns off, the display may momentarily become
abnormal screen.
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3.7 Backlight Connector Pin Configuration
Note 1
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Note 2
Note 3
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Input Interface for LIPS board
CN1 :EL7H001ZZ2 (JAE)
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4. Optical Specification
Optical characteristics are determined after the unit has been `ON' and stable for approximately 45 minutes
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