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Model Name: T460HW04 V8
Issue Date : 2010/09/17
( )Preliminary Specifications
( )Final Specifications
Contents
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No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT SPECIFICATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DEFINITION OF LABEL
8-2 PACKING METHODS
8-3 PALLET AND SHIPMENT INFORMATION
9 PRECAUTION
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECT FILM
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Record of Revision
Version Date Page Description
1.0 2010/09/02 First release
2.0 2010/09/10 Update Min. Luminance
3.0 2010/09/17 Update 3.7.2 Backlight Power Sequence
1. General Description
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This specification applies to the 46.0 inch Color TFT-LCD Module T460HW04 V8. This LCD module has a
TFT active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 46.0 inch. This module
supports 1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are
arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit gray
scale signal for each dot.
The T460HW04 V8 has been designed to apply the 8-bit 2 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are
very important.
* General Information
Items Specification Unit Note
Active Screen Size 46.00 inch
Display Area 1018.08(H) x 572.67(V) mm
Outline Dimension 1076.5(H) x 634.7(V) x 22.4(D) mm D: front bezel to T-con cover
Driver Element a-Si TFT active matrix
Bezel Opening 1024.5 (H) x 578.7 (V) mm
Display Colors 8 bit, 16.7M Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.53025 (H) x 0.53025 (W) mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment HC, 3H Hard Coating
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2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the
unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
o
Storage Temperature TST -20 +60 [ C] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
o
Panel Surface Temperature PST 65 [ C] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
Note 4: Storage period should refer to RA criteria
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3. Electrical Specification
The T460HW04 V8 requires two power inputs. One is employed to power the LCD electronics and to drive the
TFT array and liquid crystal. The second input for BLU is to power inverter.
3.1 Electrical Characteristics
3.1.1: DC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD -- 1.32 1.45 A 1
Power Consumption PC -- 15.84 17.40 Watt 1
Inrush Current IRUSH -- -- 4 A 2
Input Differential Voltage VID 200 400 600 mVDC 3
LVDS Differential Input High Threshold Voltage VTH +100 -- +300 mVDC 3
Interface
Differential Input Low Threshold Voltage VTL -300 -- -100 mVDC 3
Input Common Mode Voltage VICM 1.1 1.25 1.4 VDC 3
FDIM_IN 140 -- 240 Hz 4
DIM_IN
DCR DDIM_IN 5 -- 100 % 4
Interface FDIM_OUT -- 180 -- Hz 4
DIM_OUT
DDIM_OUT 5 -- 100 % 4
VIH
CMOS Input High Threshold Voltage 2.7 -- 3.3 VDC 5
(High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.6 VDC 5
(Low)
Backlight Power Consumption PBL -- 105.6 117.8 Watt
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3.1.2: AC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
Receiver Clock : Spread Spectrum Fclk Fclk
Fclk_ss -- MHz 6
Modulation range -3% +3%
Receiver Clock : Spread Spectrum
LVDS Fss 30 -- 200 KHz 6
Modulation frequency
Interface
Receiver Data Input Margin
Fclk = 85 MHz tRMG -0.4 -- 0.4 ns 7
Fclk = 65 MHz -0.5 -- 0.5
Note :
1. VDD = 12.0V, Fv = 60Hz, Fclk= 82MHz , 25 , Test Pattern : White Pattern
2. Measurement condition : Rising time = 400us
9''
*1'
s
3. VICM = 1.25V
LVDS -
V IC M V TH
|V ID |
V TL
LVDS +
GND
|V ID |
0V
|V ID |
4. DCR Interface: Function Table
Input Output
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DCR_Enable DIM_IN DIM_OUT
High PWM Input DCR Dimming Out
Low PWM Input PWM Input
NC NC Keep High
Note.(4-1) : During the deep duty control, partial darkness or center darkness might happen
due to insufficient lamp current.
Note.(4-2): At low temperature, more warm up time may be needed.
5. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM.
6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
)66
)FONBVVPD[
)FONBVVPD[
)FON
)FONBVVPLQ
)FONBVVPLQ
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7. Receiver Data Input Margin
Rating
Parameter Symbol Unit Note
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz T=1/Fclk
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG| 2T/7 2T/7+|tRMG| ns
Input Data Position3 tRIP5 3T/7-|tRMG| 3T/7 3T/7+|tRMG| ns
Input Data Position4 tRIP4 4T/7-|tRMG| 4T/7 4T/7+|tRMG| ns
Input Data Position5 tRIP3 5T/7-|tRMG| 5T/7 5T/7+|tRMG| ns
Input Data Position6 tRIP2 6T/7-|tRMG| 6T/7 6T/7+|tRMG| ns
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
/9'65[
5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[
,QSXW 'DWD
/9'65[
,QSXW &ORFN 9GLII 9
)FON 7
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3.2 Interface Connections
z LCD connector: FI-RE51S-HF (JAE, LVDS connector)
z Mating connector:
PIN Symbol Description PIN Symbol Description
1 VDD Power Supply, +12V DC Regulated 26 CH2_0+ LVDS Channel 2, Signal 0+
2 VDD Power Supply, +12V DC Regulated 27 CH2_1- LVDS Channel 2, Signal 1-
3 VDD Power Supply, +12V DC Regulated 28 CH2_1+ LVDS Channel 2, Signal 1+
4 VDD Power Supply, +12V DC Regulated 29 CH2_2- LVDS Channel 2, Signal 2-
5 VDD Power Supply, +12V DC Regulated 30 CH2_2+ LVDS Channel 2, Signal 2+
6 NC No connection 31 GND Ground
7 GND Ground 32 CH2_CLK- LVDS Channel 2, Clock -
8 GND Ground 33 CH2_CLK+ LVDS Channel 2, Clock +
9 GND Ground 34 GND Ground
10 CH1_0- LVDS Channel 1, Signal 0- 35 CH2_3- LVDS Channel 2, Signal 3-
11 CH1_0+ LVDS Channel 1, Signal 0+ 36 CH2_3+ LVDS Channel 2, Signal 3+
12 CH1_1- LVDS Channel 1, Signal 1- 37 Reserved AUO Internal Use Only
13 CH1_1+ LVDS Channel 1, Signal 1+ 38 Reserved AUO Internal Use Only
14 CH1_2- LVDS Channel 1, Signal 2- 39 GND Ground
15 CH1_2+ LVDS Channel 1, Signal 2+ 40 SCL EEPROM Serial Clock
16 GND Ground 41 SDA EEPROM Serial Data
17 CH1_CLK- LVDS Channel 1, Clock - 42 NC No connection
EEPROM Write Protection
18 CH1_CLK+ LVDS Channel 1, Clock + 43 WP High(3.3V) for Writable,
Low(GND) for Protection
19 GND Ground 44 Panel_SEL reserve 0603 footprint of resistor to ground
Open/High(3.3V) for NS,
20 CH1_3- LVDS Channel 1, Signal 3- 45 LVDS_SEL
Low(GND) for JEIDA
21 CH1_3+ LVDS Channel 1, Signal 3+ 46 NC No connection
22 Reserved AUO Internal Use Only 47 NC No connection
23 Reserved AUO Internal Use Only 48 NC No connection
24 GND Ground 49 NC No connection
25 CH2_0- LVDS Channel 2, Signal 0- 50 NC No connection
51 Reserved AUO Internal Use Only
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