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Spec. No.: DDPM-ES05-0.1
Version: 2
Total pages: 28
Date: 2003-May-09
AU OPTRONICS CORPORATION
Product Specifications
17.0" SXGA Color TFT-LCD Module
Model Name: M170ES05
V.2
Approved by Prepared by
DDBU Marketing Division / AU Optronics Croporation
Customer Checked & Approved by
(C) Copyright AU Optronics, Inc. 1/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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Product Specifications
17.0" SXGA Color TFT-LCD Module
Model Name: M170ES05
V.2
( ) Preliminary Specifications
( ) Final Specifications
Note: This Specification is subject to change without notice.
(C) Copyright AU Optronics, Inc. 2/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Display Characteristics
2.2 Functional Block Diagram
2.3 Optical Characteristics
2.4 Pixel format image
3.0 Electrical characteristics
3.1 Absolute Maximum Ratings
3.2 Connectors
3.3 Signal Pin & Description
3.4 RSDS Signal Electrical Characteristic
3.5 Timing Requirement
3.6 Electrical Rating
3.7 Power ON/OFF Sequence
4.0 Backlight Characteristics
4.1 Signal for Lamp connector
4.2 Parameter guide line for CCFL Inverter
5.0 Vibration, shock and drop
5.1 Vibration and shock
5.2 Drop test
6.0 Environment
6.1 Temperature and humidity
6.1.1 Operating conditions
6.1.2 Shipping conditions
6.2 Atmospheric pressure
6.3 Thermal shock
7.0 Reliability
7.1 Failure criteria
7.2 Failure rate
7.2.1 Usage
7.2.2 Components de-rating
7.3 CCFL life
7.4 ON/OFF cycle
8.0 Safety
8.1 Sharp edge requirement
8.2 Material
8.2.1 Toxicity
8.2.2 Flammability
8.3 Capacitors
8.4 Hazardous voltage
9.0 Other requirements
9.1 Smoke free design
9.2 National test lab requirement
10.0 Mechanical Characteristics
(C) Copyright AU Optronics, Inc. 3/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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ii Record of Revision
Version and Date Page Old description New Description Remark
0.1 2003/5/09 All First Edition for Customer All
(C) Copyright AU Optronics, Inc. 4/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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1.0 Handling Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when
handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface
Connector of the TFT-LCD module.
10) After installation of the TFT-LCD module into an enclosure (LCD monitor housing, for example), do not
twist nor bend the TFT -LCD module even momentary. At designing the enclosure, it should be taken into
consideration that no bending/twisting forces are applied to the TFT -LCD module from outside.
Otherwise the TFT -LCD module may be damaged.
(C) Copyright AU Optronics, Inc. 5/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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General Description
This specification applies to the 17.0 inch Color TFT-LCD Module M170ES05.
The display supports the SXGA (1280(H) x 1024(V)) screen format and 262K colors (RGB 6-bits data).
All input signals are 2 Channel RSDS interface compatible.
This module does not contain an inverter card for backlight.
2.1 Display Characteristics
The following items are characteristics summary on the table under 25 condition:
ITEMS Unit SPECIFICATIONS
Screen Diagonal [mm] 432(17.0")
Active Area [mm] 337.920 (H) x 270.336(V)
Pixels H x V 1280(x3) x 1024
Pixel Pitch [mm] 0.264 (per one triad) x 0.264
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
2
White Luminance [cd/m ] 300 (center) @ 7mA
( )
Contrast Ratio 450 : 1 (Typ)
Optical Response Time
p p [msec] 16 (Typ.)
( yp )
Color Saturation 72% NTSC
NTSC
Nominal Input Voltage VDD [Volt] +5.0 V
Power Consumption [Watt] 25W (w/o Inverter, All black pattern) (typ.)
(VDD line + CCFL line)
Weight [Grams] 2000 (Typ)
Physical Size [mm] 358.5(W) x 296.5(H) x 19.0(D)
Electrical Interface Front R/G/B data (6bits) and clock pairs
Back R/G/B data (6bits) and clock pairs
7 timing control signal input
4 DC power input
Support Color 262k colors (RGB 6-bit data )
Temperature Range
o
Operating [ C] 0 to +50
o
Storage (Shipping) [ C] -20 to +60
(C) Copyright AU Optronics, Inc. 6/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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2.2 Functional Block Diagram
The following diagram shows the functional block of the 17.0 inches Color TFT-LCD Module:
D
D
FPC
FPC 3
3
8
8
4
4
H X6~X10 0
0
I
AR Back Differential
O
FS
7 EP
3 - Pairs Signals
Pairs
Back LVDS Signals
RSDS Signals 0 FT
1 HW
-- FPC
FPC
A1
22O
G
13
T0
p
i
n TFT-LCD
s S
oS
o TFT-LCD
FPC
FPC u
r
c
u
r
c
1280*(3)*102
1280*(3)*1024
ee
X1~X5
X1~X5 DD 4
Front Differential
Front Differential
r
ir
v
e
i
v Pixels
Pixels
FrontLVDS Signals
RSDS Signals Pairs Signals re
r
H Pairs Signals I
CI
C
I
R FPC
FPC
AO
FS
7 P Gamma
E
5 -
0 T
F
1 W Correction
Countrol Signals -H
LVDS Signals A O
2-
1
G2
15 FPC
FPC
T0 DC-DC
DC-DC
p
i
n
s Converter D
D Gate Driver IC
1
1
DC Input
+5V LVDS Signals G1
G1 Gate Driver IC G1024
G1024
X
PCB DC
Inverter 4 CCFL
power
P-TWO AF7301-A2G1T JST BHR-04VS-1
&
P-TWO AF7501-A2G1T Mating Type: SM04(4.0)B-BHS-1-TB
(C) Copyright AU Optronics, Inc. 7/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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2.3 Optical Characteristics
The optical characteristics are measured under stable conditions at 25 (Room Temperature):
Item Unit Conditions Min. Typ. Max.
Horizontal (Right) 60 70 -
CR = 10 (Left) 60 70
Vertical (Up) 60 70 -
CR = 10 (Down) 60 70
Viewing Angle (Note 4) [degree]
Horizontal (Right) 70 80 -
CR = 5 (Left) 70 80 -
Vertical (Up) 70 80 -
CR = 5 (Down) 70 80 -
Contrast ratio Normal Direction 250 450 -
Raising Time - 4 5
Response Time (Note 1) [m sec] Falling Time - 12 20
Raising + Falling - 16 25
Red x 0.61 0.64 0.67
Red y 0.31 0.34 0.37
Color / Chromaticity Green x 0.26 0.29 0.32
Coordinates (CIE) Green y 0.58 0.61 0.64
Blue x 0.11 0.14 0.17
Blue y 0.04 0.07 0.10
White x 0.28 0.31 0.34
Color Coordinates (CIE) White
White y 0.30 0.33 0.36
2
White Luminance @ CCFL 7.0mA [cd/m ] 230 300 -
(center)
Luminance Uniformity (Note 2) [%] 75 80 -
Cross-talk (in 75Hz) (Note 5) [%] 1.5
Note 1: Definition of Response time:
f time:
The output signals of photo detector are measured when the input signals are changed from " Black" to " White"
(falling time), and from "White" to " Black" (rising time), respectively. The response time is interval between the 10%
and 90% of amplitudes.
TrR
%
TrD
100
90
Optical
Response
10
white white
0
black
(C) Copyright AU Optronics, Inc. 8/28
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Note 2: Brightness uniformity of these 9 points is defined as below:
90 % 50 % 10 %
10 %
50 %
90 %
Minimum Luminance in 9 Points (1-9)
Uniformity = ----------------------------------------
Maximum Luminance in 9 Points (1-9)
Note 3: TCO '99 Certification Requirements and test methods for environmental labeling of Display Report No. 2
defines Luminance uniformity as below:
((Lmax,+30deg. / Lmin,+30deg.) + (Lmax,-30deg. / Lmin,-30deg.)) / 2
This panel is compatible with TCO99 approbation in luminance uniformity <1.7, luminance contrast >0.5
Note 4: Viewing angle definition
(C) Copyright AU Optronics, Inc. 9/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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Note 5:
1/2 1/6 2/3 1/2 1/3 1/6
1/6
A A' 1/6
1/3
1/2 1/2
B B'
2/3
184 gray level 184 gray level
0 gray level
Unit: percentage of dimension of display area
l LA-LA' l / LA x 100%= 1.5% max., LA and LB are brightness at location A and B
l LB-LB' l / LB x 100%= 1.5% max., LA' and LB' are brightness at location A' and B'
2.4: Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format.
1 2 1279 1280
1st Line R G B R G B R GB R G B
1024th R G B R G B R GB R G B
(C) Copyright AU Optronics, Inc. 10/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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3.0 Electrical characteristics
3.1 Absolute Maximum Ratings
Absolute maximum ratings of the module is as following:
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VIN -0.3 +5.5 [Volt]
CCFL Inrush current ICFLL - 38 [mA]
CCFL Current ICFL - 7.6 [mA] rms
o
Operating Temperature TOP 0 +50 [ C] Note 1
Operating Humidity HOP 8 95 [%RH] Note 1
o
Storage Temperature TST -20 +60 [ C] Note 1
Storage Humidity HST 8 95 [%RH] Note 1
Note 1 : Maximum Wet-Bulb should be 39 and No condensation.
Relative Humidity %
Twb=39
T=40 ,H=95%
100
95
80
T=50 ,H=55%
60
T=60 ,H=39%
Storage
40 Operation range T=65 ,H=29%
range
20
Storage
5
0
-20 0 50 60
o
Temperature C
(C) Copyright AU Optronics, Inc. 11/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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3.2 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
X-PCBA
Connector Name J1 J2
Manufacture P-TWO ( ) P-TWO ( )
or compatible or compatible
Type Part Number AF7501-A2G1T AF7301-A2G1T
(FH12-50S-0.5H) (FH12-30S-0.5H)
CCFL
Connector Name Lamp Connector / Backlight lamp
Manufacturer JST
Type Part Number BHR-04VS-1
Mating Type Part Number SM04(4.0)B-BHS-1-TB
Connector Diagram: Rear view of LCM
P 30F -TWO P-TWO 50F
#1 #30 #1 J1 #50
J2
3.3 Signal Pin & Description
Connector J1
Pin NO. Symbol Description
1 GND Ground
2 FB[0]N Front side blue RSDS signal pair 0 negative data
3 FB[0]P Front side blue RSDS signal pair 0 positive data
4 GND Ground
5 FB[1]N Front side blue RSDS signal pair 1 negative data
6 FB[1]P Front side blue RSDS signal pair 1 positive data
7 GND Ground
8 FB[2]N Front side blue RSDS signal pair 2 negative data
9 FB[2]P Front side blue RSDS signal pair 2 positive data
10 GND Ground
11 FG[0]N Front side green RSDS signal pair 0 negative data
(C) Copyright AU Optronics, Inc. 12/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
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12 FG[0]P Front side green RSDS signal pair 0 positive data
13 GND Ground
14 FG[1]N Front side green RSDS signal pair 1 negative data
15 FG[1]P Front side green RSDS signal pair 1 positive data
16 GND Ground
17 FG[2]N Front side green RSDS signal pair 2 negative data
18 FG[2]P Front side green RSDS signal pair 2 positive data
19 GND Ground
20 FCLKN Front side RSDS clock negative
21 FCLKP Front side RSDS clock positive
22 GND Ground
23 FR[0]N Front side red RSDS signal pair 0 negative data
24 FR[0]P Front side red RSDS signal pair 0 positive data
25 GND Ground
26 FR[1]N Front side red RSDS signal pair 1 negative data
27 FR[1]P Front side red RSDS signal pair 1 positive data
28 GND Ground
29 FR[2]N Front side red RSDS signal pair 2 negative data
30 FR[2]P Front side red RSDS signal pair 2 positive data
31 GND Ground
32 FXDIO Front side source driver IC start pulse signal
Latch the polarity of source outputs and switch the new data to source
33 XSTB
outputs
34 POL Source driver IC output polarity control
35 BXDIO Back side Source driver IC start pulse signal
36 GND Ground
37 YCLK Gate driver IC clock in
38 YDIO Gate driver IC start pulse
39 YOE Gate driver IC output enable signal
40 NC -
41 GND Ground
42 NC -
43 NC -
44 VDD 5V input Voltage
45 GND Ground
46 VDD 5V input Voltage
47 VDD 5V input Voltage
(C) Copyright AU Optronics, Inc. 13/28
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48 VDD 5V input Voltage
49 ID1 Maker ID bit1 (Ground)
50 ID0 Maker ID bit0 (Ground)
Connector J2
Pin NO. Symbol Description
1 GND Ground
2 BB[0]N Back side blue RSDS signal pair 0 negative data
3 BB[0]P Back side blue RSDS signal pair 0 positive data
4 GND Ground
5 BB[1]N Back side blue RSDS signal pair 1 negative data
6 BB[1]P Back side blue RSDS signal pair 1 positive data
7 GND Ground
8 BB[2]N Back side blue RSDS signal pair 2 negative data
9 BB[2]P Back side blue RSDS signal pair 2 positive data
10 GND Ground
11 BG[0]N Back side green RSDS signal pair 0 negative data
12 BG[0]P Back side green RSDS signal pair 0 positive data
13 GND Ground
14 BG[1]N Back side green RSDS signal pair 1 negative data
15 BG[1]P Back side green RSDS signal pair 1 positive data
16 GND Ground
17 BG[2]N Back side green RSDS signal pair 2 negative data
18 BG[2]P Back side green RSDS signal pair 2 positive data
19 GND Ground
20 BCLKN Back side RSDS clock negative
21 BCLKP Back side RSDS clock positive
22 GND Ground
23 BR[0]N Back side red RSDS signal pair 0 negative data
24 BR[0]P Back side red RSDS signal pair 0 positive data
25 GND Ground
26 BR[1]N Back side red RSDS signal pair 1 negative data
27 BR[1]P Back side red RSDS signal pair 1 positive data
28 GND Ground
29 BR[2]N Back side red RSDS signal pair 2 negative data
30 BR[2]P Back side red RSDS signal pair 2 positive data
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3.4 RSDS signal electrical characteristic
RSDS Characteristics
Parameter Symbol Min. Typ. Max. Unit Conditions
RSDS high input voltage VIHRSDS 100 200 - mV VCMRSDS = + 1.2 V
RSDS low input voltage VILRSDS - - 200 - 100 mV VCMRSDS = + 1.2 V
(1) (2)
RSDS common mode VCMRSDS 0.5 - 1.4 V VDIFFRSDS = 200 mV
input voltage range (minimum value)
(3)
RSDS input leakage IDL -10 - 10 uA DxxP,DxxN,CLKP,CLKN
current
Notes:
1. VCMRSDS = (VCLKP + VCLKN) / 2 or VCMRSDS = (VDxxP + VDxxN) / 2
2. VDIFFRSDS = VCLKP - VCLKN or VDIFFRSDS = VDxxP - VDxxN
The typical RSDS swing level of peak to peak is 400mV.
3. DxxP/N=Differential inputs for 6-bit RGB data
CLKP/N= Differential inputs for clock data
VRSDSN
VIL RSDS
VCM RSDS
VIH RSDS
VRSDSP
GND
(V RSDSP)-(V RSDSN)
VIH RSDS
0V
VIL RSDS
RSDS signal definition
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3.5 Timing Requirement
This following data describes the source and gate drivers timing requirement for 17" SXGA (1280 1024) Panel. The
control timing is defined based on VESA SXGA standard(non-interlaced). The symbols and timing requirement are defined in
Table 1 and Table 2. And, the timing diagrams for the source and gate drivers are shown in Figure 1 Figure 2 and Figure 3
respectively.
Source Driver IC (Horizontal Timing)
Table 1.
- Unit
Item Symbol
Min. Typ. Max.
Last Data Timing TLDT 1 14 - CLKPperiod
XDIO Pulse Width PWXDIO 1 1.6 2 CLKPperiod
XSTB-XDIO Time TSTB-XDIO 5 92 - CLKPperiod
XSTB Pulse Width PWSTB 5(?) 80 - CLKPperiod
POL-XSTB Time TPOL-STB 14 (15 - ns(CLKPperiod)
CLKPperiod)
XSTB-XPOL Time TSTB-POL 10 (11 - ns(CLKPperiod)
CLKPperiod)
XSTB-CLK Time TSTB -CLKP-N
(90%) 4 - ns
(50%)
XDIO setup time TSETUP2 2 - - ns
XDIO hold time THOLD2 4 - - ns
Data setup time TSETUP1 3 - - ns
Data hold time THOLD1 1 - - ns
Clock pulse low period PWCLK(L) 6 - - ns
Clock pulse high period PWCLK(H) 6 - - ns
Clock Pulse Frequency FCLK 40 54 67.5 MHz
width Period PWCLK 14.81 18.52 20 ns
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FCLKP-FCLKN
BCLKP-BCLKN
TLDT PW XDIO
FXDIO
TSTB-XDIO
BXDIO
FR[X]P-FR[X]N Even Odd Even Odd Even Odd Even Odd Even Odd
FG[X]P-FG[X]N 638 638 639 639 0 0 1 1 2 2
FB[X]P-FB[X]N 640th 1st 2nd
Data Data Data
BR[X]P-BR[X]N Even Odd Even Odd Even Odd Even Odd Even Odd
BG[X]P-BG[X]N 1278 1278 1279 1279 640 640 641 641 642 642
BB[X]P-BB[X]N 1280th 641th 642th
Data Data Data
XSTB PW STB
POL Invalid Valid Invalid
T POL-STB T STB-POL
Figure 1
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CLKP-CLKN VIH RSDS
(RSDS) VCM RSDS
VIL RSDS
TSETUP2
THOLD2 T SETUP1 TSETUP1 PWCLK(L) PWCLK(H)
90% 90% PWCLK
XDIO
THOLD1 THOLD1
R(0)P
- R(0) R(1) R(0) R(1) R(0) R(1)
VIH RSDS
VCM RSDS
R(0)N VIL RSDS
R(1)P
- R(2) R(3) R(2) R(3) R(2) R(3) R(2)
R(1)N
R(2)P
- R(4) R(5) R(4) R(5) R(4) R(5) R(4)
R(2)N
G(0)P
- G(0) G(1) G(0) G(1) G(0) G(1) G(0)
G(0)N
G(1)P
- G(2) G(3) G(2) G(3) G(2) G(3) G(2)
G(1)N
G(2)P
- G(4) G(5) G(4) G(5) G(4) G(5) G(4)
G(2)N
B(0)P
- B(0) B(1) B(0) B(1) B(0) B(1) B(0)
B(0)N
B(1)P
- B(2) B(3) B(2) B(3) B(2) B(3) B(2)
B(1)N
B(2)P
- B(4) B(5) B(4) B(5) B(4) B(5) B(4)
B(2)N
1st 2nd 3rd (0): LSB
Data Data Data (6): MSB
Figure 2
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Gate Driver IC (Vertical Timing)
Table 2.
-
Item Symbol Frame rate@60Hz Frame rate@75Hz Unit
Min. Typ. Max. Min. Typ. Max.
YDIO setup time TSDI 200 6640 - 200 5280 - ns
YDIO hold time THDI 350 9040 - 350 7200 - ns
Gate off time TGOFF - 1846 - - 1470 - ns
Gate delay time TGDLY - 282 - - 242 - ns
YOE low period TGOFF+TGDLY 1000 2128 - 1000 1712 - ns
DE
Data Line 1 Line 2 Line 3
XSTB
YCLK
YOE
YDIO
TGOFF TSDI THDI
TGDLY
Table 3
Note1 : DE is reference signal, DE means the display data valid.
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3.6 Electrical Ratings
Values
Item Symbol Unit Notes
Min Typ Max
Power Supply Input VDD 4.5 5 5.5 V(DC)
Voltage Voltage (1)
Power Supply Ripple - - 250 mVp-p
Power Supply Input Icc - 800 1000 mA 1
Current
Differential pair Zm 90 100 110 Ohm 2
Impedance Current
Power Consumption Pc 4 5 W 1
Inrush current Irush - - 5 A 3
Notes:
1. The specified current and power consumption are under the conditions (VDD=5V,T=25 ,Frame
rate=75Hz,black pattern).
2. This value is needed to a proper signal quality and is measured from Scalar Chip output pins to its
mating connector. Besides, the impedance of FPC between scalar board and LCD panel is also needed
to keep.
3. Based on AU circuit design ,the duration of the rush current is about 1 ms, which should have the
following typical condition.
5V
0.9Vcc
0.1Vcc
GND
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3.7 Power ON/OFF Sequence
The LCD module must be powered up and down as indicated or the device may be damaged permanently.
The power-on includes both system starting and from the sleep to wake-up mode ; the power-off includes
both system shunt down and the one from on to sleep. There should be no power sequence changing in the
sleep to wake-up mode.
90% 90%
10% 10%
VDD
T1 T6 T7
10% 10%
Signal
T5
T2
10% 10%
Lamp on
T3 T4
Values
Parameter Unit
Min Max
T1 0.5 10 ms
T2 0.01 30 ms
T3 170 - ms
T4 100 - ms
T5 0 - ms
T6 - - ms
T7 1000 - ms
(C) Copyright AU Optronics, Inc. 21/28
January, 2002 All Rights Reserved. M170ES05 v.2 Ver0.1
No Reproduction and Redistribution Allowed.
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4.0 Backlight Characteristics
4.1 Signal for Lamp connector
Pin # Signal Name
1 Lamp High Voltage
2 Lamp High Voltage
3 No Connection
4 Ground
4.2 Parameter guide line for CFL Inverter
Symbol Parameter Min Typ Max Units Condition
2 o
(L63) White Luminance 230 300 - [cd/m ] (Ta=25 C)
o
ISCFL CCFL standard current 6.5 7.0 7.5 [mA] (Ta=25 C)
rms
o
IRCFL CCFL operation range 3.0 7.0 7.5 [mA] (Ta=25 C)
rms
o
fCFL CCFL Frequency 40 50 80 [KHz] (Ta=25 C)
Note 1
o
ViCFL CCFL Ignition Voltage 1700 [Volt] (Ta=0 C)
o
(0 C) rms Note 2
o
ViCFL CCFL Ignition Voltage 1200 [Volt] (Ta=25 C)
o
(25 C) rms Note 2
o
VCFL CCFL Discharge Voltage 700 860 [Volt] (Ta=25 C)
(Reference) rms Note 3
o
PCFL CCFL Power consumption 19.6 25.8 [Watt] (Ta=25 C)
Note 3
Note 1: CCFL Frequency should be carefully determined to avoid interference between inverter and TFT LCD
Note 2: CCFL inverter should be able to give out a p
power that has a generating capacity of over 1700 voltage.
r
Lamp units need 1700 voltage minimum for ignition
Note 3: Calculator value for reference (ICFL