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Customer's Acceptance Specification
TO: AVNET
Accepted By: Date:
Customer's Acceptance Specification
Type 15.0 UXGA Color TFT/LCD Module
Model Name: IAUX14K
Document Control Number: CAS I-914K-AV01
Issued By: T. Tokuda Date: June 2,2003
Sales Support
International Display Technology
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 1/34
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Customer's Acceptance Specification
i Contents
i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
4.1 Luminance Uniformity
5.0 Signal Interface
5.1 Connectors
5.2 Interface Signal Connector
5.3 Interface Signal Description
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
5.4.2 LVDS Receiver Internal Circuit
5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
5.5 Signal for Lamp connector
6.0 Pixel format image
7.0 Parameter guide line for CFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Specifications
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 National Test Lab Requirement
13.0 Qualifications and CFL Life
13.1 Visual Screen Quality
13.2 Line Defect
13.3 Bright and Black Dots
13.4 CFL Life
14.0 Packaging
15.0 Label
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 2/34
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Customer's Acceptance Specification
ii Record of Revision
Date Document Revision Page Summary
October 18,2002 CAS I-914K-ID01 All First Edition for AVNET
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 3/34
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Customer's Acceptance Specification
1.0 Handling Precautions
If any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the
LCD module.
The LCD panel and the CFL are made of glass and may break or crack if dropped on a hard surface,
so please handle them with care.
CMOS-ICs are included in the LCD panel. They should be handled with care, to prevent electrostatic
discharge.
Do not press the reflector sheet at the back of the LCD module to any directions.
Do not stick the adhesive tape on the reflector sheet at the back of the LCD module.
Please handle care when mount in the system cover. Mechanical damage for lamp cable and for lamp
connector may cause safety problems.
Small amount of materials having no flammability grade is used in the LCD module. The LCD module
should be supplied by power complied with requirements of Limited Power Source (2.5, IEC60950 or
UL60950), or be applied exemption conditions of flammability requirements (4.7.3.4, IEC60950 or
UL60950) in an end product.
The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or
UL60950).
The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.
Never apply detergent or other liquid directly to the screen.
Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or
abrasives.
Do not touch the front screen surface in your system, even bezel.
The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by International Display Technology for any
infringements of patents or other right of the third partied which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of
International Display Technology or others.
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 4/34
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Customer's Acceptance Specification
2.0 General Description
This specification applies to the Type 15.0 Color TFT/LCD Module 'IAUX14K'.
This module is designed for a display unit of notebook style personal computer.
The screen format and electrical interface are intended to support the UXGA (1600(H) x 1200(V)) screen. Support
color is native 262K colors (RGB 6-bit data driver).
All input signals are LVDS (Low Voltage Differential Signaling) interface compatible.
This module does not contain an inverter card for backlight.
2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition:
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [mm] 381
Pixels H x V 1600(x3) x 1200
Active Area [mm] 304.8(H) x 228.6(V)
Pixel Pitch [mm] 0.1905(per one triad) x 0.1905
Pixel Arrangement R,G,B Vertical Stripe
Weight [grams] 690 Typ., 725 Max.
Physical Size [mm] 317.3(W) x 242.0(H) x 7.2(D) Typ./7.5(D) Max.
Display Mode Normally Black
Display Surface Treatment Anti-Glare
Support Color Native 262K colors (RGB 6-bit data driver)
White Luminance [cd/m2] (center) 200 Typ.
Contrast Ratio 400 : 1 Typ.
Optical Rise Time + Fall Time [msec] 60 Typ., 150 Max.
Nominal Input Voltage VDD [Volt] +3.3 Typ.
Power Consumption [Watt](VDD) 2.9 Typ., 3.8 Max.
Lamp Power Consumption [Watt] 4.5 Typ., (W/o inverter loss)
5.0 Max., (W/o inverter loss)
Typical Power Consumption [Watt] 7.4 Typ., 8.8 Max. (W/o inverter loss)
Electrical Interface 8 pairs LVDS (Even/Odd R/G/B Data (6bit),
3sync signals, Clock)
Temperature Range [degree C]
Operating 0 to +50
Storage (Shipping) -20 to +60
CFL Cable Length [mm] 35 Typ
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 5/34
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Customer's Acceptance Specification
2.2 Functional Block Diagram
The following diagram shows the functional block of this Type 15.0 Color TFT/LCD Module.
The first LVDS port transmits even pixels while the second LVDS port transmits odd pixels.
X-Driver
Y-Driver
< 8 pairs LVDS > LCD DRIVE
CARD
6bit color data
for R/G/B
(even/odd)
EVEN
PIXEL LCD TFT ARRAY/CELL
Controller
DTCLK(even/odd)
ODD
PIXEL
1600(R/G/B) x 1200
DSPTMG
Dual LVDS
Vsync RECEIVER
Hsync
G/A
VEEDID
CLKEEDID DC-DC
EEDID
DataEEDID Converter Backlight Unit
Chip
Ref circuit
VDD
GND Lamp Connector
LCD-DRIVE Connector JST BHSR-02VS-1 (2pin)
JAE FI-XB30S-HF10 (30pin)
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 6/34
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Customer's Acceptance Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows:
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 +4.0 V
Input Signal Voltage VIN -0.3 VDD+0.3 V
CFL Ignition Voltage Vs - +1,600 Vrms (Note 2)
CFL Current ICFL - +8 mAms
CFL Peak Inrush Current ICFLP - +20 mA
Operating Temperature TOP 0 +50 deg.C (Note 1)
Operating Relative Humidity HOP 8 95 %RH (Note 1)
Storage Temperature TST -20 +60 deg.C (Note 1)
Storage Relative Humidity HST 5 95 %RH (Note 1)
Vibration 1.5 10-200 G Hz
Shock 50 18 G ms Rectangle wave
Note 1: Maximum Wet-Bulb should be 39 degree C and No condensation.
Note 2: Duration : 50msec Max. Ta=0 degree C
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 7/34
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Customer's Acceptance Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition:
Item Conditions Specification
Typ. Note
Viewing Angle Horizontal (Right) 85 -
(Degrees) K>10 (Left) 85 -
Vertical (Upper) 85 -
K: Contrast Ratio K>10 (Lower) 85 -
Contrast ratio 300 -
Response Time Rising 30 -
(ms) Falling 30 -
Color Red x 0.569 +0.030
Chromaticity Red y 0.332 +0.030
(CIE) Green x 0.312 +0.030
Green y 0.544 +0.030
Blue x 0.149 +0.030
Blue y 0.132 +0.030
White x 0.313 +0.030
White y 0.329 +0.030
2
White Luminance (cd/m ) (center) 200 Typ. 170 Min.
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 8/34
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The following is the note for the Optical Characteristics:
Z
V ie w in g o r M ea s u rin g
D irec tio n
V ie w in g o r M e a s u rin g
D ire c tio n
-v +h
LEFT
U PPER
LO W E R R IG H T
Y
X
CENTER OF LCD
(X = 0 ,Y = 0 ,Z = 0 )
Chromaticity and White Balance are defined as the C.I.E. 1931 x,y coordinates at the center of LCD.
The Standard Equipment are as shown below table.
Item Standard Equipment
Viewing Angle MCPD-7000 by Ohtsuka Elec
Contrast MCPD-7000 by Ohtsuka Elec
Response Time BM5A by TOPCON OPTICAL Co.,Ltd.
White Luminance MCPD-7000 by Ohtsuka Elec
Luminance Uniformity MCPD-7000 by Ohtsuka Elec
Chromaticity MCPD-7000 by Ohtsuka Elec
White Balance MCPD-7000 by Ohtsuka Elec
The measurement is to be done after 30 minutes of Power-on of BackLight.
Unless otherwise specified, the ambient conditions are as following.
Ambient Temperature : 25 + 2 ( degreeC )
Ambient Humidity : 25 - 85 (%)
Atmospheric Pressure : 86.0 - 104.0 ( kPa )
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 9/34
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4.1 Luminance Uniformity
When the backlight is on with all pels in the unselected state (white), the luminance uniformity is defined as
follows;
Average luminance is defined as follows.
L1 + L2 + L3 + L4 + L5
Average Luminance =
5
Luminance variation is measured by dividing the maximum luminance values of the 13 or 5 test points by the
minimum luminance of the 13 or 5 test points.
Maximum Luminance 13 Points (L1-L13)
Luminance Uniformity =<1.65
Minimum Luminance 13 Points (L1-L13)
Maximum Luminance 5 Points (L1-L5)
Luminance Uniformity =<1.25
Minimum Luminance 5 Points (L1-L5)
Average luminance and Luminance uniformity test points
10mm
L6 L7 L8
L1 L2
300
L9 L5 L10
600
L3 L4
900
L11 L12 L13
10mm
10mm 400 800 1200 10mm
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 10/34
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Customer's Acceptance Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
Connector Name / Designation For Signal Connector
Manufacturer JAE
Type / Part Number FI-XB30S-HF10
Mating Receptacle Manufacture JAE
Mating Receptacle/Part Number FI-X30M
Connector Name / Designation For Lamp Connector
Manufacturer JST
Type / Part Number BHSR-02VS-1
Mating Type / Part Number SM02B-BHSS-1
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 11/34
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5.2 Interface Signal Connector
Pin # Signal Name Pin # Signal Name
1 GND 16 GND
2 VDD 17 ReCLKIN-
3 VDD 18 ReCLKIN+
4 VEEDID (Note 2,3) 19 GND
5 Reserved (Note 1) 20 RoIN0-
6 CLKEEDID (Note 2,4) 21 RoIN0+
7 DataEEDID (Note 2,4) 22 GND
8 ReIN0- 23 RoIN1-
9 ReIN0+ 24 RoIN1+
10 GND 25 GND
11 ReIN1- 26 RoIN2-
12 ReIN1+ 27 RoIN2+
13 GND 28 GND
14 ReIN2- 29 RoCLKIN-
15 ReIN2+ 30 RoCLKIN+
Note:
1. 'Reserved' pins are not allowed to connect any other line.
2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA
STANDARD Release A, Revision 1" and supports "EEDID version 1.3".
This module uses Serial EEPROM BR24C02FV (ROHM) or compatible as a EEDID function.
3. VEEDID power source shall be the current limited circuit which has not exceeding 1A.
TM
(Reference Document: "Enhanced Display Data Channel (E-DDC ) Proposed Standard", VESA)
4. Both CLKEEDID line and DataEEDID line are pulled-up with 10K ohm resistor to VEEDID power source line at
LCD panel, respectively.
Voltage levels of all input signals are LVDS compatible (except VDD, EEDID).
Refer to "Signal Electrical Characteristics for LVDS", for voltage levels of all input signals.
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 12/34
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5.3 Interface Signal Description
The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard.
PIN # SIGNAL NAME Description
1 GND Ground
2 VDD +3.3V Power Supply
3 VDD +3.3V Power Supply
4 VEEDID EEDID 3.3V Power Supply
5 Reserved Reserved
6 CLKEEDID EEDID Clock
7 DataEEDID EEDID Data
8 ReIN0- Negative LVDS differential data input (Even R0-R5, G0)
9 ReIN0+ Positive LVDS differential data input (Even R0-R5, G0)
10 GND Ground
11 ReIN1- Negative LVDS differential data input (Even G1-G5, B0-B1)
12 ReIN1+ Positive LVDS differential data input (Even G1-G5, B0-B1)
13 GND Ground
14 ReIN2- Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)
15 ReIN2+ Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)
16 GND Ground
17 ReCLKIN- Negative LVDS differential clock input (Even)
18 ReCLKIN+ Positive LVDS differential clock input (Even)
19 GND Ground
20 RoIN0- Negative LVDS differential data input (Odd R0-R5, G0)
21 RoIN0+ Positive LVDS differential data input (Odd R0-R5, G0)
22 GND Ground
23 RoIN1- Negative LVDS differential data input (Odd G1-G5, B0-B1)
24 RoIN1+ Positive LVDS differential data input (Odd G1-G5, B0-B1)
25 GND Ground
26 RoIN2- Negative LVDS differential data input (Odd B2-B5)
27 RoIN2+ Positive LVDS differential data input (Odd B2-B5)
28 GND Ground
29 RoCLKIN- Negative LVDS differential clock input (Odd)
30 RoCLKIN+ Positive LVDS differential clock input (Odd)
Note:
Input signals of odd and even clock shall be the same timing.
The module uses a 100ohm resistor between positive and negative data lines of each receiver input.
Even: First Pixel data
Odd : Second Pixel Data
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 13/34
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SIGNAL NAME Description
+RED 5 RED Data 5 (MSB)
+RED 4 RED Data 4
+RED 3 RED Data 3
+RED 2 RED Data 2
+RED 1 RED Data 1
+RED 0 RED Data 0 (LSB)
(EVEN/ODD)
Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data.
+GREEN 5 GREEN Data 5 (MSB)
+GREEN 4 GREEN Data 4
+GREEN 3 GREEN Data 3
+GREEN 2 GREEN Data 2
+GREEN 1 GREEN Data 1
+GREEN 0 GREEN Data 0 (LSB)
(EVEN/ODD)
Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data.
+BLUE 5 BLUE Data 5 (MSB)
+BLUE 4 BLUE Data 4
+BLUE 3 BLUE Data 3
+BLUE 2 BLUE Data 2
+BLUE 1 BLUE Data 1
+BLUE 0 BLUE Data 0 (LSB)
(EVEN/ODD)
Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data.
-DTCLK Data Clock: The typical frequency is 81MHz.
(EVEN/ODD) The signal is used to strobe the pixel + data and the + DSPTMG
+DSPTMG Display Timing:
When the signal is high, the pixel data shall be valid to be displayed.
VSYNC Vertical Sync: This signal is synchronized with -DTCLK. Both active high/low signals are
acceptable.
HSYNC Horizontal Sync: This signal is synchronized with -DTCLK. Both active high/low signals are
acceptable.
VDD Power Supply
GND Ground
VEEDID EEDID Power Supply
CLKEEDID EEDID Clock
DataEEDID EEDID Data
Note: Output signals except VEEDID, CLKEEDID and DataEEDID from any system shall be Hi-Z state when VDD is off.
(C) Copyright International Display Technology 2002 All Rights reserved
June 2, 2003 CAS I-914K-AV01 14/34
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5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
Electrical Characteristics
Parameter Symbol Min Typ Max Unit Conditions
Differential Input High Threshold Vth +100 mV Vcm=+1.2V
Differential Input Low Threshold Vtl -100 mV Vcm=+1.2V
Magnitude Differential Input Voltage |Vid| 100 600 mV
Common Mode Voltage Vcm 1.0 1.2 1.4 V Vth - Vtl = 200mV
Common Mode Voltage Offset
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