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Engineering Specification
Engineering Specification
Type 15.0 SXGA+ Color TFT/LCD Module
Model Name:ITSX95E
Document Control Number : OEM I-95E-04
Note:Specification is subject to change without notice. Consequently it is better to contact to
International Display Technology before proceeding with the design
of your product incorporating this module.
Product Development
International Display Technology
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 1/30
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Engineering Specification
i Contents
i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
5.0 Signal Interface
5.1 Connectors
5.2 Interface Signal Connector
5.3 Interface Signal Description
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
5.4.2 LVDS Receiver Internal Circuit
5.5 Inverter Signal connector
5.6 Inverter Signal Description
5.7 Inverter Signal Electrical Characteristics
6.0 Pixel format image
7.0 Interface Timings
7.1 Timing Characteristics
7.2 Timing Definition
8.0 Power Consumption
9.0 Power ON/OFF Sequence
10.0 Mechanical Characteristics
11.0 National Test Lab Requirement
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 2/30
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Engineering Specification
ii Record of Revision
Date Document Page Summary
Revision
March 27,2000 OEM95E-01 All First Edition for customer.
Based on Internal Specification EC F78950 as of March
10,2000.
August 4,2000 OEM95E-02 Based on Internal Specification EC F78951 as of July
12,2000.
6 To update Nominal Input Voltage, Logic Power
Consumption, Weight and Physical Size.
12 To add Note for Even/Odd.
14 To update LVDS Macro AC characteristics.
16,17 To update by customer required subject for Inverter
signal.
18 To update Lamp Frequency.
21 To update Timing Characteristics.
23 To update Power Consumption.
24 To update Power ON/OFF Sequence.
25,26 To update Reference Drawing as of June 5,2000.
27 To add National Test Lab Requirement.
October 10,2000 OEM95E-03 Based on Internal Specification EC F78952 as of
September 6,2000.
7 To update Functional Block Diagram.
8 To update Absolute Maximum (VDD).
9 To update Optical Characteristics.
11 To update Interface Signal Connector and add Note.
12,13 To update Interface Signal Description.
14,15,16,17,18 To update Interface Signal Electrical Characteristics.
26 To update Power Consumption.
28,29 To update Reference Drawing as of September 5,2000.
April 24,2001 OEM95E-04 Based on Internal Specification EC H30700 as of January
31,2001.
1,5,6,7 To avoid using "inch" indication.
6 To update Weight.
28,29 To update Reference Drawings.
Januray 15,2002 OEM I-95E-04 Updated by establishment of the New Company as
"International Display Technology".
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 3/30
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Engineering Specification
1.0 Handling Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth
when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) In case if a Module has to be put back into the packing container slot after once it was taken out
from the container, do not press the center of the CFL Reflector edge.
Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may
be damaged.
10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the
Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example),
do not twist nor bent the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are applied
to the TFT Module from outside. Otherwise the TFT Module may be damaged.
12) The fluorescent lamp in the liquid crystal display (LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.
13) Small amount of materials having no flammability grade is used in the LCD module.
The LCD module should be supplied by power complied with requirements of
Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption
conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product.
O The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by International Display Technology for any
infringements of patents or other right of the third partied which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of International
Display Technology or others.
O The information contained herein may be changed without prior notice. It is therefore
advisable to contact International Display Technology before proceeding with the design of
equipment incorporating this product.
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 4/30
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Engineering Specification
2.0 General Description
This specification applies to the Type 15.0 Color TFT/LCD Module 'ITSX95E'.
This module is designed for a display unit of notebook style personal computer.
The screen format and electrical interface are intended to support the SXGA+ (1400(H) x 1050(V))screen.
Support color is native 262k colors ( RGB 6-bit data driver ).
All input signals are LVDS interface compatible.This module contains an inverter card for backlight.
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 5/30
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Engineering Specification
2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition:
ITEMS SPECIFICATIONS
Screen Diagonal [mm] 381
Active Area [mm] 304.5(H) x 228.375(V)
Pixels H x V 1400(x3) x 1050
Pixel Pitch [mm] 0.2175(per one triad) x 0.2175
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
Typical White Luminance [cd/m 2]
SMData=00H: 150 Typ.(Center) 140 Typ.(5 Points average)
Contrast Ratio 200 : 1 Typ.
Optical Rise Time/Fall Time [msec] 30Typ. 50Max.(each)
Nominal Input Voltage [Volt]
VDD +3.3 Typ.
5VSUS,5VALW line +5.0 Typ.
PWR_SCR line +14.4 Typ.
Logic Power Consumption [watt] 1.8 Typ.
Backlight Power Consumption [watt]
PWR_SCR line 5.2 Typ.
SMData=00H
Weight [grams] 625( Typ.) 660(Max.)
Physical Size [mm] 317.3(W) x 242.0(H) x 10.5(D) Typ. 10.8(D)Max.
Electrical Interface (Logic) 6-bit digital video for each color R/G/B, 3 sync, Clock
(8 pairs LVDS)
Electrical Interface (Inverter) Panel IDs,SMB_CLK,SMB_DAT,FPVEE
Support Color Native 262K colors ( RGB 6-bit data driver )
Temperature Range (degree C)
Operating 0 to +50
Storage (Shipping) -20 to +60
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 6/30
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Engineering Specification
2.2 Functional Block Diagram
The following diagram shows the functional block of the 38.1cm(15.0") Color TFT/LCD Module.
X-Driver
Y-Driver
< 8 pairs LVDS > LCD DRIVE
CARD
6bit color data
for R/G/B
(even/odd)
EVEN
PIXCEL LCD TFT ARRAY/CELL
Controller
DTCLK(even/odd)
ODD
PIXCEL
1400(R/G/B) x 1050
DSPTMG
Dual LVDS
Vsync RECEIVER
Hsync
G/A
VEEDID
CLK EEDID DC-DC
EEPROM
Data EEDID Converter Backlight Unit
Ref circuit
VDD
GND
LCD-DRIVE Connector
JAE FI-XB30S-HF10 (30pin)
Inverter Connector
MOLEX 52207-1690 (16pin)
Panel IDsp
SMB_CLK
SMB_DAT
FPVEE INVERTER
PWR_SRC
5VSUS
5VALW
GND
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Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows :
Item Symbol Min Max Unit Conditions
Supply Voltage VDD -0.3 +4.0 V
5VSUS, -0.3 +5.5 V
5VALW
PWR_SRC -0.3 +25 V
Input Voltage of Signal Vin -0.3 +VDD+0.3 V
FPVEE -0.3 +5.5 V
SMB_CLK -1 +7 V
SMB_DAT
Operating Temperature TOP 0 +50 deg.C Note 1
Operating Humidity HOP 8 95 %RH Note 1
Storage Temperature TST -20 +60 deg.C Note 1
Storage Humidity HST 5 95 %RH Note 1
Vibration 1.5 10-200 G Hz
Shock 50 18 G ms Rectangle
wave
Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation.
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 8/30
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Engineering Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition:
Item Conditions Specifiation
Typ. Note
Viewing Angle Horizontal (Right) 40 -
(Degrees) K210 (Left) 40 -
Vertical (Upper) 15 -
K:Contrast Ratio K210 (Lower) 30 -
Contrast ratio 200 -
Response Time Rising 30 50(Max)
(ms) Falling 30 50(Max)
Color Red x 0.569 -
Chromaticity Red y 0.332 -
(CIE) Green x 0.312 -
Green y 0.544 -
Blue x 0.149 -
Blue y 0.132 -
White x 0.313 -
White y 0.329 -
White Luminance 150
(cd/m 2) SMData=00H Center
140
5 Points
Average
(C) Copyright International Display Technology 2002 All Rights reserved.
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Engineering Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
Connector Name / Designation For Signal Connector
Manufacturer JAE
Type / Part Number FI-XB30S-HF10
Mating Type / Part Number FI-X30M
Connector Name / Designation For Inverter Connector
Manufacturer Molex
Type / Part Number 52207-1690
Mating Type / Part Number (FPC)
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Engineering Specification
5.2 Interface Signal Connector
Pin # Signal Name Pin # Signal Name
1 FG (GND) 17 GND
2 GND 18 ReCLKIN-
3 VDD 19 ReCLKIN+
4 VDD 20 GND
5 VEEDID (Note 2,3) 21 RoIN0-
6 NC (Reserved, Note 1) 22 RoIN0+
7 CLKEEDID (Note 2,4) 23 GND
8 DataEEDID (Note 2,4) 24 RoIN1-
9 ReIN0- 25 RoIN1+
10 ReIN0+ 26 GND
11 GND 27 RoIN2-
12 ReIN1- 28 RoIN2+
13 ReIN1+ 29 GND
14 GND 30 RoCLKIN-
15 ReIN2- 31 RoCLKIN+
16 ReIN2+ 32 FG (GND)
Note:
1. 'Reserved' pins are not allowed to connect any other line.
2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA
STANDARD Release A, Revision 1" and supports "EEDID version 1.3".
This module uses Serial EEPROM BR24C02FV (ROHM) or compatible as a EEDID function.
3. VEEDID power source shall be the current limited circuit which has not exceeding 1A. (Reference Document :
"Enhanced Display Data Channel (E-DDCTM) Proposed Standard", VESA)
4. Both CLKEEDID line and DataEEDID line are pulled-up with 10K ohm resistor to VEEDID power source line at LCD
panel, respectively.
Voltage levels of all input signals are LVDS compatible (except VDD,EEDID). Refer to "Signal Electrical
Characteristics for LVDS(*)", for voltage levels of all input signals.
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 11/30
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Engineering Specification
5.3 Interface Signal Description
The module uses a pair of LVDS receiver SN75LVDS86(Texas Instruments) compatible. LVDS is a differential
signal technology for LCD interface and high speed data transfer device. Transmitter shall be
SN75LVDS84(negative edge sampling) or compatible.
PIN SIGNAL Description
# NAME
1 FG Frame Ground
2 GND Ground
3 VDD +3.3V Power Supply
4 VDD +3.3V Power Supply
5 VEEDID EEDID 3.3V Power Supply
6 Reserved Reserved
7 CLKEEDID EEDID Clock
8 DataEEDID EEDID Data
9 ReIN0- Negative LVDS differential data input (Even R0-R5, G0)
10 ReIN0+ Positive LVDS differential data input (Even R0-R5, G0)
11 GND Ground
12 ReIN1- Negative LVDS differential data input (Even G1-G5, B0-B1)
13 ReIN1+ Positive LVDS differential data input (Even G1-G5, B0-B1)
14 GND Ground
15 ReIN2- Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)
16 ReIN2+ Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)
17 GND Ground
18 ReCLKIN- Negative LVDS differential clock input (Even)
19 ReCLKIN+ Positive LVDS differential clock input (Even)
20 GND Ground
21 RoIN0- Negative LVDS differential data input (Odd R0-R5, G0)
22 RoIN0+ Positive LVDS differential data input (Odd R0-R5, G0)
23 GND Ground
24 RoIN1- Negative LVDS differential data input (Odd G1-G5, B0-B1)
25 RoIN1+ Positive LVDS differential data input (Odd G1-G5, B0-B1)
26 GND Ground
27 RoIN2- Negative LVDS differential data input (Odd B2-B5)
28 RoIN2+ Positive LVDS differential data input (Odd B2-B5)
29 GND Ground
30 RoCLKIN- Negative LVDS differential clock input (Odd)
31 RoCLKIN+ Positive LVDS differential clock input (Odd)
32 FG Frame Ground
Note:
1. Input signals of odd and even clock shall be the same timing.
2. The module uses a 100ohm resistor between positive and negative data lines of each receiver input.
3. Even : First Pixel Data, Odd : Second Pixel Data
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Engineering Specification
SIGNAL NAME Description
+RED 5 (ER5/OR5) RED Data 5 (MSB)
+RED 4 (ER4/OR4) RED Data 4
+RED 3 (ER3/OR3) RED Data 3
+RED 2 (ER2/OR2) RED Data 2
+RED 1 (ER1/OR1) RED Data 1
+RED 0 (ER0/OR0) RED Data 0 (LSB)
(EVEN/ODD)
Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data.
+GREEN 5 (EG5/OG5) GREEN Data 5 (MSB)
+GREEN 4 (EG4/OG4) GREEN Data 4
+GREEN 3 (EG3/OG3) GREEN Data 3
+GREEN 2 (EG2/OG2) GREEN Data 2
+GREEN 1 (EG1/OG1) GREEN Data 1
+GREEN 0 (EG0/OG0) GREEN Data 0 (LSB)
(EVEN/ODD)
Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel
data.
+BLUE 5 (EB5/OB5) BLUE Data 5 (MSB)
+BLUE 4 (EB4/OB4) BLUE Data 4
+BLUE 3 (EB3/OB3) BLUE Data 3
+BLUE 2 (EB2/OB2) BLUE Data 2
+BLUE 1 (EB1/OB1) BLUE Data 1
+BLUE 0 (EB0/OB0) BLUE Data 0 (LSB)
(EVEN/ODD)
Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel
data.
DTCLK Data Clock: The typical frequency is 54MHz.
(EVEN/ODD) The signal is used to strobe the pixel +data and the +DSPTMG
+DSPTMG (DSP) When the signal is high, the pixel data shall be valid to be displayed.
VSYNC (V-S) Vertical Sync: This signal is synchronized with DTCLK. Both active high/low signals
are acceptable.
HSYNC (H-S) Horizontal Sync: This signal is synchronized with DTCLK. Both active high/low
signals are acceptable.
VDD Power Supply
GND Ground
VEEDID EEDID Power Supply
CLKEEDID EEDID Clock
DataEEDID EEDID data
Note : Output signals except VEEDID ,CLKEEDID and DataEEDID from any system shall be Hi-Z state when VDD is off.
(C) Copyright International Display Technology 2002 All Rights reserved.
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Engineering Specification
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
Table . Electrical Characteristics
Parameter Symbol Min Typ Max Unit Conditions
Differential Input High Threshold Vth +100 mV
Differential Input Low Threshold Vtl -100 mV
Magnitude Differential Input Voltage |Vid| 100 600 mV
Common Mode Voltage Vcm 0.825 2.4 V
+|Vid|/2 -|Vid|/2
Common Mode Voltage Offset Vcm -50 +50 mV
Note:
O Input signals shall be low or Hi-Z state when VDD is off.
Figure. Voltage Definitions
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Engineering Specification
Table . Switching Characteristics
Parameter Symbol Min Typ Max Unit Conditions
Clock Frequency fc 51 54 57 MHz
Cycle Time tc 17.5 18.5 19.6 ns
Data Setup Time Tsu 700 ps fc = 54MHz, jitter < 50ps
Data Hold Time Thd 700 ps
Cycle modulation rate(Note) tCJavg 20 ps/clk
Note: This specification defines maximum average cycle modulation rate in peak-to-peak transition within any
100 clock cycles. This specification is applied only if input clock peak jitter within any 100 clock cycles is
greater than 300ps.
Figure . Timing Definition (Even)
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Engineering Specification
Figure. Timing Definition (Odd)
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Engineering Specification
Figure . Timing Definition(detail A)
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Engineering Specification
5.4.2 LVDS Receiver Internal Circuit
Below figure shows the internal block diagram of the LVDS receiver.
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Engineering Specification
5.5 Inverter Signal connector
Pin # Signal Name Pin # Signal Name
1 (Note*) PANEL-ID0 9 5VALW
2 PANEL-ID1 10 5VSUS
3 PANEL-ID2 11 GND
4 PANEL-ID3 12 GND
5 NC 13 GND
6 FPVEE 14 PWR_SRC
7 SMB_CLK 15 PWR_SRC
8 SMB_DAT 16 PWR_SRC
(Note*) Molex Connector No.1 Mark
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Engineering Specification
5.6 Inverter Signal Description
Input connector Typical(typ) Description
Voltage
levels
52207-1690
Molex
( FFC/FPC)
Pin Function
1* PANEL_ID0 "0" Connect to GND
2 PANEL_ID1 "1" Open
3 PANEL_ID2 "1" Open
4 PANEL_ID3 "0" Connect to GND
5 NC
Control signal input into the inverter to turn the
6 FPVEE (0,3.3V)typ
backlight ON & OFF (3.3V-ON,0V-OFF)
SMBus interface for sending brightness &
7 SMB_CLK (0V,5V)typ
contrast information to the inverter/panel
SMBus interface for sending brightness &
8 SMB_DAT (0V,5V)typ
contrast information to the inverter/panel
This should be used as power source that stores
9 5VALW 5V typ the brightness/contrast values & the circuit that
interfaces with SMB_CLK & SMB_DAT
This should be used as power source for the
10 5VSUS 4.85V to 5.2V
control circuitry on the inverter.
11 GND
12 GND
13 GND
(9V to 21V) This power rail should be used as a power rail to
14 PWR_SRC
typ drive the backlight DC-AC converter
(9V to 21V) This power rail should be used as a power rail to
15 PWR_SRC
typ drive the backlight DC-AC converter
(9V to 21V) This power rail should be used as a power rail to
16 PWR_SRC
typ drive the backlight DC-AC converter
Note (*) : Molex Connector No.1 Mark
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Engineering Specification
5.7 Inverter Signal Electrical Characteristics
Item Symbol Min. Typ. Max. UNITS CONDITION
Input Voltage PWR_SRC 9.0 14.4 21 V (Ta=25 degree C)
5VSUS, 4.85 5.0 5.2 V
5VALW
Input Power P(PWR_SRC) 5.2 5.8 W SMData=00H,
PWR_SRC=14.4V
P(5VSUS) 5 mW
P(5VALW) 5 mw
ON/OFF FPVEE 2.0 V ON
FPVEE 0.8 V OFF
Lamp Frequency F 40 68 KHz
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Engineering Specification
6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image.
Even Odd Even Odd
0 1 1398 1399
1st Line R G B R G B R G B R G B
1050th Line R G B R G B R G B R G B
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Engineering Specification
The following chart is the Luminance versus the Lamp current for your reference.(Center)
(FFH) (00H)
(SMBUS Data)
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Engineering Specification
7.0 Interface Timings
7.1 Timing Characteristics
Signal Item Symbol MIN. TYP. MAX. Unit
DTCLK Freqency Fdck 51 54 57 [MHz]
Tck 18.5 [ns]
+V-Sync Frame Rate Fv 60 [Hz]
Tv 16.67 [ms]
Nv 1058 1066 2046 [lines]
V-Active Level Tva 15.78 46.7 [us]
Nva 1 3 62 [lines]
V-Back Porch Nvb 6 12 125 [lines]
V-Front Porch Nvf 1 1 [lines]
+DSPTMG V-Line m 1050 [lines]
+H-Sync Scan Rate Fh 63.98 [KHz]
Th 15.63 [usec]
Nh 762 844 1023 [Tck]
H-Active Level Tha 1.037 [usec]
Tha 8 56 250 [Tck]
H-Back Porch Thb 26 64 300 [Tck]
H-Front Porch Thf 8 24 [Tck]
+DSPTMG Display Thd 12.96 [usec]
+DATA Data Even/Odd n 1400 [dots]
Note:Both positive Hsync and positive Vsync polarity is recommended.
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January 15,2002 OEM I-95E-04 24/30
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Engineering Specification
Typical Vertical Timing Table
Support mode Tvblk m Tvf VSYNC Tv,Nv Tva Tvb
Vertical Active Field Front Porch Frame VSYNC VSYNC
Blanking Time Width Back Porch
1400 x 1050 at 60Hz 0.250 ms 16.411 ms 0.016 ms 16.661 ms 0.047 ms 0.188 ms
(H line rate : 15.63 us) (16 lines) (1050 lines) (1 line) (1066 lines) (3 lines) (12 lines)
Typical Horizontal Timing Table
Thblk Thd Thf Th,Nh Tha Thb
Support mode
Horizontal Active Field HSYNC H Line HSYNC HSYNC
Blanking Front Porch Time Width Back Porch
1400 x 1050
2.667 us 12.963 us 0.444 us 15.630 us 1.037 us 1.185 us
Dotclock : 108.000
(288 dots) (1400 dots) (48 dots) (1688 dots) (112 dots) (128 dots)
MHz (54.000MHz x2)
7.2 Timing Definition
DSPTMG
Tv
Tvblk m
Tvf Tva Tvb
-VSYNC
+VSYNC
DSPTMG
Th
Thblk Thd
Thf Tha Thb
-HSYNC
+HSYNC
Tck
VIDEO(Even) 0 2 4 n-4 n-2
VIDEO(Odd) 1 3 5 n-3 n-1
DTCLK
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January 15,2002 OEM I-95E-04 25/30
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Engineering Specification
8.0 Power Consumption
Input power specifications are as follows;
SYMBOL PARAMETER Min Typ Max UNITS CONDITION
VDD Logic/LCD Drive 3.0 3.3 3.6 [V] Load Capacitance 40uF
Voltage
PDD VDD Power 3.2 [W] MAX. Pattern,
VDD=3.6[V]
PDD VDD Power 1.8 [W] All Black Pattern,
VDD=3.3[V]
IDD VDD Current 890 [mA] MAX Pattern,
VDD=3.6[V]
IDD VDD Current 545 [mA] All Black Pattern,
VDD=3.3[V]
VDDrp Allowable Logic/LCD 100 [mVp-p]
Drive Ripple Voltage
VDDns Allowable Logic/LCD 100 [mVp-p]
Drive Ripple Noise
MAX. Pattern : 2dot Vertical sub-pixel Stripe
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 26/30
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Engineering Specification
9.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from
any system shall be Hi-Z state or low level when VDD is off.
150ms min.
90% 90%
VDD 10% 10%
10%
0V
10ms max. 0 min.
0 min.
90% 90%
Signals 10% 10%
0V
100ms min.
20ms min.
180ms min.
1ms min. 0ms min.
30ms max.
90% 90%
PWR_SRC
10%
0V
10ms min.
0ms min.
90% 90%
5VALW/5VSUS
10%
0V
0ms min.
FPVEE
10% 10%
0V
(C) Copyright International Display Technology 2002 All Rights reserved.
January 15,2002 OEM I-95E-04 27/30
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Engineering Specification
10.0 Mechanical Characteristics
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Engineering Specification
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January 15,2002 OEM I-95E-04 29/30
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Engineering Specification
11.0 National Test Lab Requirement
The display module is authorized to Apply the UL Recognized Mark.
Conditions of Acceptability
O This component has been judged on the basis of the required spacings in the Standard for Safety of
Information Technology Equipment, Including Electrical Business Equipment, CAN/CSA C22.2 No.950-95
*UL 1950, Third Edition, including revisions through revision date March 1,1998, which are based on the
Fourth Amendment to IEC 950, Second Edition, which would cover the component itself if submitted for
Listing.
O The inverter output circuit supplied with this model is a limited Current Circuit.
O The units are supplied by Limited Power Sources.
O The terminals and connectors are suitable for factory wiring only.
O The terminals and connectors have not been evaluated for field wiring.
O A suitable Electrical and Fire enclosure shall be provided.
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