Service Manuals, User Guides, Schematic Diagrams or docs for : . Various a6m20
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5 4 3 2 1
01.BLOCK DIAGRAM
A6M
02.RESET MAP
03.CLOCK MAP
04.S1_HT_C51 REVISION: 2.0
05.S1_DDR2
06.S1_CNTL/DEBUG/THERM
07.S1_POWER
08.DDR2_SODIMM 128-BIT
D 09.DDR2 TER/FETGAGE Unbuffer D
10.C51_HT_CPU
AMD S1g1 Channel A/B DDR2
11.C51_HT_MCP 638 PIN
SO-DIMM
12.C51_PCIE PACKAGE
13.C51_VIDEO
14.C51_VCC_GND
200/400/800
HyperTransport
15.FAN/THERM SENSOR
16.MCP51_HT
17.MCP51_PCI/LPC
18.MCP51_IDE/SATA
MHz
x16
19.MCP51_USB/AC97/SMB
20.MCP51_RGMI/XTAL
21.MCP51_VCC
22.G73M_PCIE LVDS
23.G73M_FB I/F nVIDIA
24.G73M_LVDS/GND Gigabit
25.G73M_VGA/TV PCI-E x1 CRT
Ethernet C51MV
26.G73M_TMDS/GPIO RTL8111B
C 27.G73M_XTAL/ROM STRAP BGA 468
TV OUT C
28.G73M_STRAPS
29.G73M_MEM_PART1
30.G73M_MEM_PART2
200/400/800
31.HDD/CDROM
HyperTransport
32.MINI PCI
X8 /X4
33.CARD BUS
34.PCMCIA
MHz
35.1394/SD_CARD
36.SIO/SIR
PCMCIA
37.FWH
38.KBC 33MHz
33MHz
39.USB/BLUE TOOTH FWH LPC BUS 1394
40.CRT/TV CON PCI BUS R5C841
41.LVDS/INVERTER
42.ALC880 CARD READER
43.AMP nVIDIA
44.MIC/LINE-IN JACK SUPPER I/O
MINI-PCI
B 45.RJ45/11/MDC SIR MCP51 /WIRE LESS B
46.LAN LPC47N217
47.BLANK
48.FUNCTION KEY
BGA 508
49.LED
50.POWER SEQEUNCE(1) AUDIO DJ KEY
51.POWER SEQUENCE(2) KBC 38857
52.SCREW HOLE INSTANT KEY
53.Battery SATA 2 /SATA
54.CHARGE
55.BATLOW/SD#
56.LOAD SWITCH AZALIA CODEC
ALC660
57.BLANK
IDE BUS
58.BLANK
59.BLANK
CD-ROM
60.POWER SEQUENCE BLCOK Pri USB BUS
61.POWER BUDGET BLOCK MDC
62.BLANK HEADER
A A
HDD USB BLUE
Sec CCD TOOTH MiniCard
/WIRE LESS
USB 2.0 X4 final_1.00
Title : BLOCK DIAGRAM
ASUSTECH CO.,LTD. Engineer: Jefing_Li
Size Project Name Rev
C A6M 1.0
Date: Friday, March 10, 2006 Sheet 1 of 73
5 4 3 2 1
5 4 3 2 1
SKT638 S1 CPU
RESET MAP
D D
RESET#
PWROK
G73M C51MV
CPU_PWROK
HT_CPU_PWRGD
CPU_RESET#
HT_CPU_RST#
C C
PE_RESET# PCIE RST*
HT_MCP_PWRGD
HT_MCP_RESET#
MCP51
PWRBTN#
PWRBTN# HT_MCP_RST#
POWER SWTCH RSTBTN# HT_MCP_RST#
RSTBTN# HT_MCP_PWRGD
RESET Button KBRST# HT_MCP_PWRGD
KBC KBRDRSTIN#
MINI_PCI_RST#
HT_VLD PCI RST0#
B HT_VLD CARD_PCI_RST# B
HTVDD_EN PCI RST1#
HTVDD_EN LAN_PCI_RST#
CPU_VLD PCI RST2#
CPU_VLD PCI_IDE_RST#
CPUVDD_EN PCI RST3#
CPUVDD_EN LPC_RST#
PWRGD LPC_RST#
PWRGD
SUSB#
SLP_S3# AC_RESET#
MEM_VLD AC_RESET#
MEM VLD
SUSC# SIO FLASH KBC IDE 88E8001. CARDBUS MINI PCI
SLP_S5#
PWRGD_SB
PWRGD_SB
CD ROM
MDC
AUDIO
A A
final_1.00
Title : RESET MAP
ASUSTECH CO.,LTD. Engineer: Jefing_Li
Size Project Name Rev
A3 A6T 1.0
Date: Monday, March 06, 2006 Sheet 2 of 73
5 4 3 2 1
5 4 3 2 1
CLOCK MAP
SKT638 S1 CPU
2
HT_CPU_RXCLK0 MEMORY_A_CLK[2:1]
D HT_CPU_RXCLK0*
HT_CPU_TXCLK0
MEMORY_A_CLK[2:1]* 2 D
HT_CPU_TXCLK0*
HT_CPU_RXCLK1
HT_CPU_RXCLK1*
HT_CPU_TXCLK1 2
G73M
HT_CPU_TXCLK1*
MEMORY_B_CLK[2:1]
MEMORY_B_CLK[2:1]* 2
CPUCLK_IN*
CPUCLK_IN SO-DIMM 0
CLKOUT_200MHZ C51M SO-DIMM 1
CLKOUT_200MHZ*
HT_CPU_RXCLK1*
HT_CPU_RXCLK1
HT_CPU_TXCLK1*
HT_CPU_TXCLK1
PE0_REFCLK
HT_CPU_RXCLK0* PE0_REFCLK*
HT_CPU_RXCLK0
C HT_CPU_TXCLK0*
HT_CPU_TXCLK0 PE1_REFCLK
C
PE1_REFCLK*
HT_MCP_RXCLK0
HT_MCP_RXCLK0* PE2_REFCLK
HT_MCP_TXCLK0 PE2_REFCLK*
HT_MCP_TXCLK0*
CLKIN_25MHZ XTAL_IN
CLKIN_200MHZ* XTAL_OUT
CLKIN_200MHZ
14.31818MHZ
MCPCLK_OUT MCP51M BUF_SIO SIO
MCPCLK_OUT*
SUSCLK
25MHZ_CLKOUT LPC_CLK0
33MHZ MINI PCI
B B
PCI_CLK0
33MHZ
HT_MCP_RXCLK0* PCI_CLK1
HT_MCP_RXCLK0 PCI_CLK2 R5C841
HT_MCP_TXCLK0* PCI_CLK3
HT_MCP_TXCLK0 PCI_CLK4 CARDBUS
PCI_CLK_FB
CONTROLLER
33MHZ
LPC_CLK1 KBC
FLASH 88E8001
32.768 KHZ RTC_XTAL
BUF_25MHZ
MII_RXCLK
XTAL_IN MII_TXCLK
25.0 MHZ
AC_BITCLK
XTAL_OUT AC_BITCLK MDC
A A
24MHZ
ALC880 final_1.00
Title : CLOCK MAP
ASUSTECH CO.,LTD. Engineer: Jefing_Li
Size Project Name Rev
A3 A6T 1.0
Date: Monday, March 06, 2006 Sheet 3 of 73
5 4 3 2 1
5 4 3 2 1
U1A
HT_CPU_TX_CLK_H1 J5 Y4 HT_CPU_RX_CLK_H1
[10] HT_CPU_TX_CLK_H1 HT_CPU_TX_CLK_L1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_RX_CLK_L1 HT_CPU_RX_CLK_H1 [10]
[10] HT_CPU_TX_CLK_L1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CPU_RX_CLK_L1 [10]
+1.2V_HT HT_CPU_TX_CLK_H0 J3 Y1 HT_CPU_RX_CLK_H0
[10] HT_CPU_TX_CLK_H0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CPU_RX_CLK_H0 [10]
D [10] HT_CPU_TX_CLK_L0
HT_CPU_TX_CLK_L0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 HT_CPU_RX_CLK_L0
HT_CPU_RX_CLK_L0 [10] D
R401 1 2 49.9Ohm HT_CPU_TX_CTL_H1 P3 T5 HT_CPU_RX_CTL_H1 T4011 N/A TPC26T
R402 1 HT_CPU_TX_CTL_L1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CPU_RX_CTL_L1
2 49.9Ohm P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 T4021 N/A TPC26T
HT_CPU_TX_CTL_H0 N1 R2 HT_CPU_RX_CTL_H0
[10] HT_CPU_TX_CTL_H0 HT_CPU_TX_CTL_L0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_RX_CTL_L0 HT_CPU_RX_CTL_H0 [10]
[10] HT_CPU_TX_CTL_L0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CPU_RX_CTL_L0 [10]
HT_CPU_TX_CAD_H15 N5 T4 HT_CPU_RX_CAD_H15
HT_CPU_TX_CAD_L15 L0_CADIN_H15 L0_CADOUT_H15 HT_CPU_RX_CAD_L15
LAYOUT: PLACE NEAR CPU P5 L0_CADIN_L15 L0_CADOUT_L15 T3
HT_CPU_TX_CAD_H14 M3 V5 HT_CPU_RX_CAD_H14
STUFF WHEN CONFIGURED AS HT_CPU_TX_CAD_L14 M4
L0_CADIN_H14 L0_CADOUT_H14
U5 HT_CPU_RX_CAD_L14
HT_CPU_TX_CAD_H13 L0_CADIN_L14 L0_CADOUT_L14 HT_CPU_RX_CAD_H13
16-BIT LINK L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CPU_RX_CAD_L[0..15] [10]
HT_CPU_TX_CAD_L13 M5 V3 HT_CPU_RX_CAD_L13
HT_CPU_TX_CAD_H12 L0_CADIN_L13 L0_CADOUT_L13 HT_CPU_RX_CAD_H12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
HT_CPU_TX_CAD_L12 K4 W5 HT_CPU_RX_CAD_L12
HT_CPU_TX_CAD_H11 L0_CADIN_L12 L0_CADOUT_L12 HT_CPU_RX_CAD_H11 HT_CPU_RX_CAD_H[0..15] [10]
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
HT_CPU_TX_CAD_L11 H4 AA5 HT_CPU_RX_CAD_L11
HT_CPU_TX_CAD_H10 L0_CADIN_L11 L0_CADOUT_L11 HT_CPU_RX_CAD_H10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
HT_CPU_TX_CAD_L10 H5 AB3 HT_CPU_RX_CAD_L10
HT_CPU_TX_CAD_H9 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_RX_CAD_H9
[10] HT_CPU_TX_CAD_L[0..15] F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
HT_CPU_TX_CAD_L9 F4 AC5 HT_CPU_RX_CAD_L9
HT_CPU_TX_CAD_H8 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_RX_CAD_H8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
HT_CPU_TX_CAD_L8 F5 AD3 HT_CPU_RX_CAD_L8
[10] HT_CPU_TX_CAD_H[0..15] L0_CADIN_L8 L0_CADOUT_L8
HT_CPU_TX_CAD_H7 HYPERTRANSPORT HT_CPU_RX_CAD_H7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
HT_CPU_TX_CAD_L7 N2 R1 HT_CPU_RX_CAD_L7
HT_CPU_TX_CAD_H6 L0_CADIN_L7 L0_CADOUT_L7 HT_CPU_RX_CAD_H6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
HT_CPU_TX_CAD_L6 M1 U3 HT_CPU_RX_CAD_L6
HT_CPU_TX_CAD_H5 L0_CADIN_L6 L0_CADOUT_L6 HT_CPU_RX_CAD_H5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
HT_CPU_TX_CAD_L5 HT_CPU_RX_CAD_L5
C HT_CPU_TX_CAD_H4
L2
J1
L0_CADIN_L5 L0_CADOUT_L5 U1
W2 HT_CPU_RX_CAD_H4 C
HT_CPU_TX_CAD_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CPU_RX_CAD_L4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
HT_CPU_TX_CAD_H3 G1 AA2 HT_CPU_RX_CAD_H3
HT_CPU_TX_CAD_L3 L0_CADIN_H3 L0_CADOUT_H3 HT_CPU_RX_CAD_L3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
HT_CPU_TX_CAD_H2 G3 AB1 HT_CPU_RX_CAD_H2
HT_CPU_TX_CAD_L2 L0_CADIN_H2 L0_CADOUT_H2 HT_CPU_RX_CAD_L2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
HT_CPU_TX_CAD_H1 E1 AC2 HT_CPU_RX_CAD_H1
HT_CPU_TX_CAD_L1 L0_CADIN_H1 L0_CADOUT_H1 HT_CPU_RX_CAD_L1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
HT_CPU_TX_CAD_H0 E3 AD1 HT_CPU_RX_CAD_H0
HT_CPU_TX_CAD_L0 L0_CADIN_H0 L0_CADOUT_H0 HT_CPU_RX_CAD_L0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
SOCKET638
Do not cross plane.
U1E
P20 RSVD_MA0_CLK_H3 RSVD_MA_RESET_L H16
P19 RSVD_MA0_CLK_L3 RSVD_MB_RESET_L B18
N20 RSVD_MA0_CLK_H0
N19 RSVD_MA0_CLK_L0 RSVD_VIDSTRB1 B3
RSVD_VIDSTRB0 C1
H6
B RSVD_VDDNB_FB_H
RSVD_VDDNB_FB_L G6 B
RSVD_CORE_TYPE D5
MISC
FREE5 R24
INTERNAL W18
FREE6
R26 RSVD_MB0_CLK_H3 FREE4 R23
R25 RSVD_MB0_CLK_L3 FREE1 AA8
P22 RSVD_MB0_CLK_H0 FREE2 H18
R22 RSVD_MB0_CLK_L0 FREE3 H19
SOCKET638
A A
final_1.00
Title : S1_HT_C51
ASUSTECH CO.,LTD. Engineer: Jefing_Li
Size Project Name Rev
A3 A6T 1.0
Date: Thursday, March 09, 2006 Sheet 4 of 73
5 4 3 2 1
5 4 3 2 1
MEM_MA0_CLK_H2 MEM_MB0_CLK_H2
[8] MEM_MA0_CLK_H2 [8] MEM_MB0_CLK_H2
1
1
C501 C502
MEM_MA0_CLK_L2 the cap close to cpu less than 1200mil MEM_MB0_CLK_L2
[8] MEM_MA0_CLK_L2 [8] MEM_MB0_CLK_L2
2
2
1.5PF/50V max neckdown to & from caps is 500mil 1.5PF/50V
MEM_MA0_CLK_H1 MEM_MB0_CLK_H1
[8] MEM_MA0_CLK_H1 [8] MEM_MB0_CLK_H1
1
1
C503 C504
D [8] MEM_MA0_CLK_L1
MEM_MA0_CLK_L1
[8] MEM_MB0_CLK_L1
MEM_MB0_CLK_L1
D
2
2
1.5PF/50V 1.5PF/50V
U1B U1C
MEM_MA_DATA[0..63] [8] MEM_MB_DATA[0..63] [8]
MEM_MA0_CLK_H2 Y16 MEM_MB0_CLK_H2 AF18
MEM_MA0_CLK_L2 MA0_CLK_H2 MEM_MB0_CLK_L2 MB0_CLK_H2
AA16 MA0_CLK_L2 AF17 MB0_CLK_L2
MEM_MA0_CLK_H1 E16 AA12 MEM_MA_DATA63 MEM_MB0_CLK_H1 A17 AD11 MEM_MB_DATA63
MEM_MA0_CLK_L1 MA0_CLK_H1 MA_DATA63 MEM_MA_DATA62 MEM_MB0_CLK_L1 MB0_CLK_H1 MB_DATA63 MEM_MB_DATA62
[8,9] MEM_MA0_CS_L[0..3] F16 MA0_CLK_L1 MA_DATA62 AB12 [8,9] MEM_MB0_CS_L[0..3] A18 MB0_CLK_L1 MB_DATA62 AF11
AA14 MEM_MA_DATA61 AF14 MEM_MB_DATA61
MEM_MA0_CS_L3 MA_DATA61 MEM_MA_DATA60 MEM_MB0_CS_L3 MB_DATA61 MEM_MB_DATA60
V19 MA0_CS_L3 MA_DATA60 AB14 Y26 MB0_CS_L3 MB_DATA60 AE14
MEM_MA0_CS_L2 J22 W11 MEM_MA_DATA59 MEM_MB0_CS_L2 J24 Y11 MEM_MB_DATA59
MEM_MA0_CS_L1 MA0_CS_L2 MA_DATA59 MEM_MA_DATA58 MEM_MB0_CS_L1 MB0_CS_L2 MB_DATA59 MEM_MB_DATA58
V22 MA0_CS_L1 MA_DATA58 Y12 W24 MB0_CS_L1 MB_DATA58 AB11
MEM_MA0_CS_L0 T19 AD13 MEM_MA_DATA57 MEM_MB0_CS_L0 U23 AC12 MEM_MB_DATA57
[8,9] MEM_MA0_ODT[0..1] MA0_CS_L0 MA_DATA57 MEM_MA_DATA56 [8,9] MEM_MB0_ODT[0..1] MB0_CS_L0 MB_DATA57 MEM_MB_DATA56
MA_DATA56 AB13 MB_DATA56 AF13
MEM_MA0_ODT1 V20 AD15 MEM_MA_DATA55 MEM_MB0_ODT1 W23 AF15 MEM_MB_DATA55
MEM_MA0_ODT0 MA0_ODT1 MA_DATA55 MEM_MA_DATA54 MEM_MB0_ODT0 MB0_ODT1 MB_DATA55 MEM_MB_DATA54
U19 MA0_ODT0 MA_DATA54 AB15 W26 MB0_ODT0 MB_DATA54 AF16
AB17 MEM_MA_DATA53 AC18 MEM_MB_DATA53
MEM_MA_CAS_L MA_DATA53 MEM_MA_DATA52 MEM_MB_CAS_L MB_DATA53 MEM_MB_DATA52
[8,9] MEM_MA_CAS_L U20 MA_CAS_L MA_DATA52 Y17 [8,9] MEM_MB_CAS_L V26 MB_CAS_L MB_DATA52 AF19
MEM_MA_WE_L U21 Y14 MEM_MA_DATA51 MEM_MB_WE_L U22 AD14 MEM_MB_DATA51
[8,9] MEM_MA_WE_L MEM_MA_RAS_L MA_WE_L MA_DATA51 MEM_MA_DATA50 [8,9] MEM_MB_WE_L MEM_MB_RAS_L MB_WE_L MB_DATA51 MEM_MB_DATA50
[8,9] MEM_MA_RAS_L T20 MA_RAS_L MA_DATA50 W14 [8,9] MEM_MB_RAS_L U24 MB_RAS_L MB_DATA50 AC14
W16 MEM_MA_DATA49 AE18 MEM_MB_DATA49
[8,9] MEM_MA_BANK[0..2] MEM_MA_BANK2 MA_DATA49 MEM_MA_DATA48 [8,9] MEM_MB_BANK[0..2] MEM_MB_BANK2 MB_DATA49 MEM_MB_DATA48
K22 MA_BANK2 MA_DATA48 AD17 K26 MB_BANK2 MB_DATA48 AD18
MEM_MA_BANK1 R20 Y18 MEM_MA_DATA47 MEM_MB_BANK1 T26 AD20 MEM_MB_DATA47
MEM_MA_BANK0 MA_BANK1 MA_DATA47 MEM_MA_DATA46 MEM_MB_BANK0 MB_BANK1 MB_DATA47 MEM_MB_DATA46
[8,9] MEM_MA_CKE[0..1] T22 MA_BANK0 MA_DATA46 AD19 [8,9] MEM_MB_CKE[0..1] U26 MB_BANK0 MB_DATA46 AC20
AD21 MEM_MA_DATA45 AF23 MEM_MB_DATA45
MEM_MA_CKE1 MA_DATA45 MEM_MA_DATA44 MEM_MB_CKE1 MB_DATA45 MEM_MB_DATA44
J20 MA_CKE1 MA_DATA44 AB21 H26 MB_CKE1 MB_DATA44 AF24
MEM_MA_CKE0 MEM_MA_DATA43 MEM_MB_CKE0 MEM_MB_DATA43
C [8,9] MEM_MA_ADD[0..15] J21 MA_CKE0 MA_DATA43 AB18
AA18 MEM_MA_DATA42 [8,9] MEM_MB_ADD[0..15] J23 MB_CKE0 MB_DATA43 AF20
AE20 MEM_MB_DATA42 C
MEM_MA_ADD15 MA_DATA42 MEM_MA_DATA41 MEM_MB_ADD15 MB_DATA42 MEM_MB_DATA41
K19 MA_ADD15 MA_DATA41 AA20 J25 MB_ADD15 MB_DATA41 AD22
MEM_MA_ADD14 K20 MEMORY Y20 MEM_MA_DATA40 MEM_MB_ADD14 J26 MEMORY AC22 MEM_MB_DATA40
MEM_MA_ADD13 MA_ADD14 MA_DATA40 MEM_MA_DATA39 MEM_MB_ADD13 MB_ADD14 MB_DATA40 MEM_MB_DATA39
V24 MA_ADD13 INTERFACE MA_DATA39 AA22 W25 MB_ADD13 INTERFACE MB_DATA39 AE25
MEM_MA_ADD12 K24 Y22 MEM_MA_DATA38 MEM_MB_ADD12 L23 AD26 MEM_MB_DATA38
MEM_MA_ADD11 MA_ADD12 MA_DATA38 MEM_MA_DATA37 MEM_MB_ADD11 MB_ADD12 MB_DATA38 MEM_MB_DATA37
L20 MA_ADD11 MA_DATA37 W21 L25 MB_ADD11 MB_DATA37 AA25
MEM_MA_ADD10 R19 W22 MEM_MA_DATA36 MEM_MB_ADD10 U25 AA26 MEM_MB_DATA36
MEM_MA_ADD9 MA_ADD10 MA_DATA36 MEM_MA_DATA35 MEM_MB_ADD9 MB_ADD10 MB_DATA36 MEM_MB_DATA35
L19 MA_ADD9 MA_DATA35 AA21 L24 MB_ADD9 MB_DATA35 AE24
MEM_MA_ADD8 L22 AB22 MEM_MA_DATA34 MEM_MB_ADD8 M26 AD24 MEM_MB_DATA34
MEM_MA_ADD7 MA_ADD8 MA_DATA34 MEM_MA_DATA33 MEM_MB_ADD7 MB_ADD8 MB_DATA34 MEM_MB_DATA33
L21 MA_ADD7 MA_DATA33 AB24 L26 MB_ADD7 MB_DATA33 AA23
MEM_MA_ADD6 M19 Y24 MEM_MA_DATA32 MEM_MB_ADD6 N23 AA24 MEM_MB_DATA32
MEM_MA_ADD5 MA_ADD6 MA_DATA32 MEM_MA_DATA31 MEM_MB_ADD5 MB_ADD6 MB_DATA32 MEM_MB_DATA31
M20 MA_ADD5 MA_DATA31 H22 N24 MB_ADD5 MB_DATA31 G24
MEM_MA_ADD4 M24 H20 MEM_MA_DATA30 MEM_MB_ADD4 N25 G23 MEM_MB_DATA30
MEM_MA_ADD3 MA_ADD4 MA_DATA30 MEM_MA_DATA29 MEM_MB_ADD3 MB_ADD4 MB_DATA30 MEM_MB_DATA29
M22 MA_ADD3 MA_DATA29 E22 N26 MB_ADD3 MB_DATA29 D26
MEM_MA_ADD2 N22 E21 MEM_MA_DATA28 MEM_MB_ADD2 P24 C26 MEM_MB_DATA28
MEM_MA_ADD1 MA_ADD2 MA_DATA28 MEM_MA_DATA27 MEM_MB_ADD1 MB_ADD2 MB_DATA28 MEM_MB_DATA27
N21 MA_ADD1 MA_DATA27 J19 P26 MB_ADD1 MB_DATA27 G26
MEM_MA_ADD0 R21 H24 MEM_MA_DATA26 MEM_MB_ADD0 T24 G25 MEM_MB_DATA26
MA_ADD0 MA_DATA26 MEM_MA_DATA25 MB_ADD0 MB_DATA26 MEM_MB_DATA25
MA_DATA25 F22 MB_DATA25 E24
MEM_MA_DQS_H7 W12 F20 MEM_MA_DATA24 MEM_MB_DQS_H7 AF12 E23 MEM_MB_DATA24
MEM_MA_DQS_L7 MA_DQS_H7 MA_DATA24 MEM_MA_DATA23 MEM_MB_DQS_L7 MB_DQS_H7 MB_DATA24 MEM_MB_DATA23
W13 MA_DQS_L7 MA_DATA23 C23 AE12 MB_DQS_L7 MB_DATA23 C24
MEM_MA_DQS_H6 Y15 B22 MEM_MA_DATA22 MEM_MB_DQS_H6 AE16 B24 MEM_MB_DATA22
[8] MEM_MA_DQS_H[0..7] MEM_MA_DQS_L6 MA_DQS_H6 MA_DATA22 MEM_MA_DATA21 [8] MEM_MB_DQS_H[0..7] MEM_MB_DQS_L6 MB_DQS_H6 MB_DATA22 MEM_MB_DATA21
W15 MA_DQS_L6 MA_DATA21 F18 AD16 MB_DQS_L6 MB_DATA21 C20
MEM_MA_DQS_H5 AB19 E18 MEM_MA_DATA20 MEM_MB_DQS_H5 AF21 B20 MEM_MB_DATA20
MEM_MA_DQS_L5 MA_DQS_H5 MA_DATA20 MEM_MA_DATA19 MEM_MB_DQS_L5 MB_DQS_H5 MB_DATA20 MEM_MB_DATA19
[8] MEM_MA_DQS_L[0..7] AB20 MA_DQS_L5 MA_DATA19 E20 [8] MEM_MB_DQS_L[0..7] AF22 MB_DQS_L5 MB_DATA19 C25
MEM_MA_DQS_H4 AD23 D22 MEM_MA_DATA18 MEM_MB_DQS_H4 AC25 D24 MEM_MB_DATA18
MEM_MA_DQS_L4 MA_DQS_H4 MA_DATA18 MEM_MA_DATA17 MEM_MB_DQS_L4 MB_DQS_H4 MB_DATA18 MEM_MB_DATA17
AC23 MA_DQS_L4 MA_DATA17 C19 AC26 MB_DQS_L4 MB_DATA17 A21
MEM_MA_DQS_H3 G22 G18 MEM_MA_DATA16 MEM_MB_DQS_H3 F26 D20 MEM_MB_DATA16
MEM_MA_DQS_L3 MA_DQS_H3 MA_DATA16 MEM_MA_DATA15 MEM_MB_DQS_L3 MB_DQS_H3 MB_DATA16 MEM_MB_DATA15
G21 MA_DQS_L3 MA_DATA15 G17 E26 MB_DQS_L3 MB_DATA15 D18
MEM_MA_DQS_H2 C22 C17 MEM_MA_DATA14 MEM_MB_DQS_H2 A24 C18 MEM_MB_DATA14
B MEM_MA_DQS_L2 C21
MA_DQS_H2
MA_DQS_L2
MA_DATA14
MA_DATA13 F14 MEM_MA_DATA13 MEM_MB_DQS_L2 A23
MB_DQS_H2
MB_DQS_L2
MB_DATA14
MB_DATA13 D14 MEM_MB_DATA13 B
MEM_MA_DQS_H1 G16 E14 MEM_MA_DATA12 MEM_MB_DQS_H1 D16 C14 MEM_MB_DATA12
MEM_MA_DQS_L1 MA_DQS_H1 MA_DATA12 MEM_MA_DATA11 MEM_MB_DQS_L1 MB_DQS_H1 MB_DATA12 MEM_MB_DATA11
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