Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6380
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5 4 3 2 1
MS-6380 ATX Title Page
AMD PGA 462 Processor Cover Sheet 1 Pull-up Resistors 47
VIA VT8366 / VT8233 Chipset
D D
Block Diagram 2 BULK / Decoupling 48
Winbond 83627HF-AW LPC I/O GPIO SPEC 3 HISTORY 49
AMD 462 PGA Socket 4,5
Clock Synthesizer 6
VT8366 7,8,9
System Memory 10,11,12
DDR Terminations 13,14
AGP PRO SLOT 15
VT8233 16,17,18
PCI Connectors 19,20,21
CNR RISER 22
C C
AC'97 Codec 23
Audio Amplifier / Audio Port 24,25
IDE RAID Controller / Connectors 26,27
ATA 66/100 Connectors 28
USB 2.0 Host Controller 29
Front USB Port 30
Rear USB Port 31
LPC I/O 32
Hardware monitor 33
B
System ROM 34 B
Keyboard/Mouse Connectors 35
LPT/COM Port 36
Game Port 37
Smart Diagnostic LED 38
VRM 9.0/ SC2422 39
CPU Ratio Setting 40
VID Control 41
DDR Power Regulators 42
AGP Voltage Regulators 43
A
Power Mangement 44 A
PowerOK Circuit 45
Front Panel 46
Micro Star Restricted Secret
Title Rev
Cover Sheet
Document Number 10A
MS-6380
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Thursday, August 30, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 50
5 4 3 2 1
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Block
Diagram
AMD Socket 462
D D
FSB
A DDR
AGP 4X /Fast Write
G
C
P VT8366 C
P
R
6 PCI Slots
O
VLINK
Dual ATA 100
PCI-33
VT8233
B B
USB 2.0 USB 2.0 Host LPC BUS
PORT X4 Controller
IDE RAID
Controller
IEEE 802.3MAC( MII)
SUPER I/O ROM
C
USB
N
R
AC-LINK
X BUS
AC'97 Codec
A A
Dual USB 1.1 OHCI 6 Ports
Micro Star Restricted Secret
Title Rev
Block Diagram
Document Number 10A
MS-6380
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Thursday, August 30, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 2 of 50
5 4 3 2 1
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GPIO FUNCTION
VT8233 GPIO Function Define W627HF-AW
PIN NAME Function define PIN NAME Function define PIN NAME Function define
D D
GPO0 (VSUS33) GPO0 GPI0 GPI0 GP23/PLED PLED(POWER LED)
GPO1/SUSA#(VSUS33) SUSA# GPI1 ATADET0=>Detect IDE1 ATA100/66 GP24/WDTO DLED2
GPO2/SUSB#(VSUS33) SUSB# GPI2/EXTSMI# EXTSMI# GP32/PWROK DLED1
GPO3/SUSST1#(VSUS33) SUSST1# GPI3/RING# RING# GP33/RSMRST# DLED4
GPO4/SUSCLK(VSUS33) SUSCLK GPI4/LID# ATADET1=>Detect IDE2 ATA100/66 GP34/CIRRX DLED3
GPO5/CPUSTP# CPUSTP# GPI5/BATLOW# Exteranl Pull up to 3VDUAL GP35/SUSLED SUSLED
GPO6/PCISTP# PCISTP# GPI6/PME# PME#
GPO7/SLP# SLP# GPI7/SMBALRT# Exteranl Pull up to 3VDUAL PCI
DDR_SET1 => adjust
GPO8/GPI8/IPBIN0 DDR voltage from Bios GPI16/INTRUDER# Exteranl Pull down DEVICES INT# IDSEL REQ#/GNT# CLOCK
DDR_SET2 => adjust
GPO9/GPI9/IPBIN1 DDR voltage from Bios GPI17/CPUMISS Exteranl Pull up to 3VDUAL INT#A PREQ#0
C PCI SLOT 1 INT#B AD16 PCICLK1 C
INT#C PGNT#0
GPO10/GPI10/IPBRDFR GPI10(PRI_DOWN) GPI18/AOLGP1/THRM# THRM# INT#D
4CH_CTRL 4CH_CTRL: 0=>4 Channel
GPO11/GPI11/IPBRDCK 1=>2 Channel GPI19/IORDY Exteranl Pull up to VCC3 INT#B PREQ#1
PCI SLOT 2 INT#C AD17 PCICLK2
INT#D PGNT#1
GPO12/GPI12/IPBOUT0 GPO12 INT#A
DDR Voltage SET1 SET2
GPO13/GPI13/IPBOUT1 GPO13 INT#C PREQ#2
PCI SLOT 3 INT#D AD18 PCICLK3
2.5V 1 1 INT#A PGNT#2
GPO14/GPI14/IPBTDFR GPO14 INT#B
2.6V 0 1
GPO15/GPI15/IPBTDCK GPO15 2.7V 1 0 INT#D PCIREQ#3
PCI SLOT 4 INT#A AD19 PCICLK4
2.8V 0 0 INT#B PCIGNT#3
GPO16/SA16/STRAP CPU FID0 Strapping INT#C
GPO17/SA17/STRAP CPU FID1 Strapping INT#A PCIREQ#4
PCI SLOT 5 INT#B AD20 PCICLK5
INT#C PCIGNT#4
GPO18/SA18/STRAP CPU FID2 Strapping INT#D
B GPO19/SA19/STRAP CPU FID3 Strapping INT#B PCIREQ#5 B
PCI SLOT 6 INT#C AD21 PCICLK6
GPO20/GPI20 INT#D PCIGNT#5
/ACSDIN2/PCS0#/EI GPO20 INT#A
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN# GPO21 INT#A PCIREQ#6
USB 2.0 HC INT#B AD22 USB_PCLK
INT#C PCIGNT#6
GPO22/GPI22/IOR# GPO22
IDE RAID HC INT#B AD23 PCIREQ#7 ATAPCLK
GPO23/GPI23/IOW# GPO23 PCIGNT#7
GPO24/GPI24/GPIOA GPO24 CPU RATIO ADJUST==>RATIO_0 1394 LINK INT#C AD24 PCIREQ#8 1394PCLK
PCIGNT#8
GPO25/GPI25/GPIOC GPO25 CPU RATIO ADJUST==>RATIO_1
GPO26/GPI26/SMBDT2
(VSUS33) SMBDATA2/Slave SMBUS
GPO27/GPI27/SMBCK2
(VSUS33) SMBCLK2/Slave SMBUS
GPO28/GPI28/ GPO30 1==>Ratio setting by Bios;
APICD0/APICCS# 0==>Auto from CPU
GPO29/GPI29/ GPO31 0=>Vcore setting by Bios;
A APICD1/APICACK# 1=>Auto from CPU A
GPO30/GPI30/GPIOD GPO30 CPU RATIO ADJUST==>RATIO_2
Micro Star Restricted Secret
GPO31/GPI31/GPIOE GPO31 CPU RATIO ADJUST==>RATIO_3 Title Rev
GPIO Spec.
Document Number 10A
MS-6380
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Thursday, August 30, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 50
5 4 3 2 1
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SOCKET 462 Part 1
**All CPU interface are 2.5V tolerant**
VCORE
VCC3
CPU1A
SDATA#[0..63] SDATA#0 AA35 AE1 A20M# CPURST# VCORE DBREQ# R33 510
7 SDATA#[0..63] SDATA0 A20M A20M# 16
SDATA#1 W37 AG1 FERR
SDATA#2 SDATA1 FERR CPUINIT#
W35 SDATA2 INIT AJ3 R47
SDATA#3 INTR CPUINIT# 16
Y35 AL1 C37 4.7K
SDATA#4 SDATA3 INTR IGNNE# INTR 16 PLLTEST# R37 510
U35 SDATA4 IGNNE AJ1 104P R57
SDATA#5 U33 AN3 NMI IGNNE# 16
SDATA5 NMI NMI 16 680
SDATA#6 S37 AG3 CPURST# RN2
SDATA#7 SDATA6 RESET SMI# CPURST# 44 FERR# CPU_TCK
S33 AN5 FERR# 16 1 2
D
SDATA#8 SDATA7 SMI STPCLK# SMI# 16 CPU_TMS
D
AA33 AC1 3 4
SDATA#9 SDATA8 STPCLK STPCLK# 16 Q19 CPU_TRST#
AE37 SDATA9 5 6
SDATA#10 AC33 AE3 FERR CPU_TDI 7 8
SDATA#11 SDATA10 PWROK K7PWRGD 45
AC37 2N3904S
SDATA#12 SDATA11 8P4R-510
Y37
SDATA#13 SDATA12 APICCLK_CPU
AA37 SDATA13 PICCLK N1 APICCLK_CPU 6
SDATA#14 AC35 N3 APICD0# VCORE
SDATA#15 SDATA14 PICD0/BYPASSCLK APICD1# APICD0# 16
S35 SDATA15 PICD1/BYPASSCLK N5 APICD1# 16
SDATA#16 Q37
SDATA#17 SDATA16 COREFB#
Q35 SDATA17 COREFB- AG13 COREFB# 39
SDATA#18 N37 AG11 COREFB R68
SDATA#19 SDATA18 COREFB+ COREFB 39
J33 SDATA19 100
SDATA#20 G33 AN17 CPUCLK_R for test only 0.6 * VCORE
SDATA#21 SDATA20 CLKIN CPUCLK#_R VCC3
G37 SDATA21 AL17
SDATA#22 CLKIN VREF_SYS
SDATA#23
E37 SDATA22 Pull to 2.5V
G35 SDATA23 RSTCLK AN19
SDATA#24 Q33 AL19
SDATA#25 SDATA24 RSTCLK APICD0# R66 330
N33 SDATA25 C46 C45 R69
SDATA#26 L33 AL21 CLKOUT APICD1# R62 330 103P 104P 100
SDATA#27 SDATA26 K7CLKOUT CLKOUT#
N35 AN21
SDATA#28 SDATA27 K7CLKOUT
L37 SDATA28
SDATA#29 J37 VCORE
SDATA29 C32
SDATA#30 A37 AJ13 X_39P
SDATA#31 SDATA30 ANALOG R65 R61
E35 SDATA31
SDATA#32 E31 AA5 VREFMODE
SDATA#33 SDATA32 SYSVREFMODE VREF_SYS 1K 1K
E29 SDATA33 VREF_SYS W5
SDATA#34 A27 R78 R81 VCORE
SDATA34 6 CPUCLK
SDATA#35 A25 AC5 ZN 100 100
SDATA#36 SDATA35 ZN ZP C66
E21 AE5
SDATA#37 SDATA36 ZP CPUCLK_R R82 60.4RST
C C23 SDATA37
C
SDATA#38 C27 AJ25 PLLBP#
SDATA#39 SDATA38 PLLBYPASS 680P
A23 SDATA39 PLLBYPASSCLK AN15
SDATA#40 A35 AL15
SDATA#41 SDATA40 PLLBYPASSCLK
C35 SDATA41 R85
SDATA#42 C33 AN13 PLLMON1 VCORE 301RST
SDATA#43 SDATA42 PLLMON1 PLLMON2
C31 AL13
SDATA#44 SDATA43 PLLMON2 PLLTEST#
A29 AC3 R77 R80
SDATA#45 SDATA44 PLLTEST VCORE C72
C29 100 100 C39
SDATA#46 SDATA45 CPUCLK#_R R87 60.4RST
E23
SDATA#47 SDATA46 SCANCLK1 225P
C25 S1
SDATA#48 SDATA47 SCANCLK1 SCANCLK2 COREFB R64 10K 680P
SDATA#49
E17 SDATA48 SCANCLK2 S5 close Socket 462
E13 S3 SINTVAL
SDATA#50 SDATA49 SCANINTEVAL 6 CPUCLK#
E11 Q5 SSHIFTEN C40
SDATA#51 SDATA50 SCANSHIFTEN
C15 SDATA51
SDATA#52 106P/0805
E9 AA1
SDATA#53 SDATA52 DBRDY DBREQ# COREFB# R67 10K VCORE
A13 AA3
SDATA#54 SDATA53 DBREQ FLUSH#
C9 AL3
SDATA#55 SDATA54 FLUSH
A9 C43
SDATA#56 SDATA55 CPU_TCK
C21 Q1
SDATA#57 SDATA56 TCK CPU_TDI X_105P
A21 SDATA57 U1 R34
SDATA#58 TDI for internal
E19 SDATA58 U5
SDATA#59 TDO CPU_TMS X_1K
C19 Q3 VREFSYS
SDATA#60 SDATA59 TMS CPU_TRST#
C17 SDATA60 TRST U3
SDATA#61 A11 VREFMODE
SDATA#62 SDATA61
A17 SDATA62
SDATA#63 A15 L1 VID0 VCORE
SDATA63 VID0 VID0 41
L3 VID1 RN9 R30
VID1 VID1 41
L5 VID2 CPUINIT# 1 2 270
VID2 VID2 41
DICLK#[0..3] DICLK#0 W33 L7 VID3 IGNNE# 3 4
B 7 DICLK#[0..3] DICLK#1 SDATAINCLK0 VID3 VID3 41 B
J35 J7 VID4 CPURST# 5 6
DICLK#2 SDATAINCLK1 VID4 VID4 41
E27 A20M# 7 8
DICLK#3 SDATAINCLK2
E15 SDATAINCLK3
W1 FID0 8P4R-680 VREFMODE=Low=No voltage scaling
DIVAL# FID0 FID1 FID0 40
7 DIVAL# AN33 W3 FID1 40
SDATAINVAL FID1 FID2 RN10
FID2 Y1 FID2 40
DOCLK#[0..3] DOCLK#0 AE35 Y3 FID3 STPCLK# 1 2
7 DOCLK#[0..3] SDATAOUTCLK0 FID3 FID3 40 VCORE
DOCLK#1 C37 INTR 3 4
DOCLK#2 SDATAOUTCLK1 NMI
A33 5 6
DOCLK#3 SDATAOUTCLK2 SMI# ZN R38 40.2RST
C11 SDATAOUTCLK3 SCHECK0 U37 7 8
Y33
DOVAL# SCHECK1 8P4R-680 ZP R39 40.2RST
AL31 L35
SDTATOUTVAL SCHECK2
E33
AIN#0 SCHECK3 FLUSH# R56 680
AJ29 E25
AIN#1 SADDIN0 SCHECK4 PLLBP#
AL29
SADDIN1 SCHECK5
A31 R99 680 match the transmission line
7 AIN#[2..14] AIN#[2..14] AIN#2 AG33 C13 Push-pull compensation circuit
AIN#3 SADDIN2 SCHECK6 PLLMON1 R72 56
AJ37 SADDIN3 SCHECK7 A19
AIN#4 AL35 PLLMON2 R70 56
AIN#5 SADDIN4
AE33 SADDIN5 SADDOUT0 J1
AIN#6 AJ35 J3 VCORE
AIN#7 SADDIN6 SADDOUT1 AOUT#2 AOUT#[2..14] RN24
AG37 C7 AOUT#[2..14] 7
AIN#8 SADDIN7 SADDOUT2 AOUT#3
AL33 A7 1 2
AIN#9 SADDIN8 SADDOUT3 AOUT#4 RN30 CLKOUT
AN37 SADDIN9 SADDOUT4 E5 3 4
AIN#10 AL37 A5 AOUT#5 AIN#0 1 2 CLKOUT# 5 6
AIN#11 SADDIN10 SADDOUT5 AOUT#6 AIN#1
AG35 SADDIN11 SADDOUT6 E7 3 4 7 8
AIN#12 AN29 C1 AOUT#7 DOVAL# 5 6
AIN#13 SADDIN12 SADDOUT7 AOUT#8 FILVAL# 8P4R-100
AN35 C5 7 8
AIN#14 SADDIN13 SADDOUT8 AOUT#9
AN31 C3
SADDIN14 SADDOUT9 AOUT#10 8P4R-270
SADDOUT10
G1 * Trace lengths of CLKOUT
A
7 AICLK# AJ33 E1 AOUT#11 A
SADDINCLK SADDOUT11
A3 AOUT#12 and -CLKOUT are between
CFWDRST SADDOUT12 AOUT#13
7 CFWDRST CONNECT
AJ21 CLKFWDRST SADDOUT13 G5 2" and 3"
AL23 G3 AOUT#14
7 CONNECT CONNECT SADDOUT14
7 PROCDRY
PROCDRY
FILVAL#
AN23 PROCRDY RN1
Micro Star Restricted Secret
AJ31 E3 AOCLK# 7
SFILLVAL SADDOUTCLK SSHIFTEN Title Rev
1 2
N12-4620011-F02 SCANCLK1 3 4 SOCKET 462 Part 1
SINTVAL 5 6 Document Number 10A
SCANCLK2 7 8 MS-6380
MICRO-STAR INT'L Last Revision Date:
8P4R-10K CO.,LTD. Thursday, August 30, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 50
5 4 3 2 1
A
B
C
D
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