Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6507E
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8 7 6 5 4 3 2 1
Version 1.0
MS-6507E
INTEL (R) Brookdale-E Chipset
03/19/2002 Update
Cover Sheet
Block Diagram
1
2
D
Willamette/Northwood 478pin mPGA-B Processor Schematics Power Delivery Map 3
D
GPIO Spec. 4
CPU:
Willamette/Northwood mPGA-478B Processor Clock ICS950213AF & ATA100 IDE CONNECTORS 5
mPGA478-B INTEL CPU Sockets 6-7
System Brookdale-E Chipset: INTEL Brookdale-E MCH -- North Bridge 8-9
INTEL MCH (North Bridge) + DDR DIMMM1,2 10
INTEL ICH4 (South Bridge)
DDR Damping & DDR Termination 11
On Board Chipset:
INTEL ICH4 -- South Bridge 12-13
C
BIOS -- FWH C
Ac'97 Codec and Audio Connector & Game Port 14
LPC Super I/O -- W83627HF
AGP 4X SLOT (1.5V) 15
Clock Generator -- CY28349
PCI SLOT 1 & 2 & 3 16
AC'97 Codec -- AvanceLogic AC201A/AC202A
Realtek RTL8101L LAN 17
Onboard Lan Chipset-- RealTek RTL8101L
LPC I/O W83627HF 18
Expansion Slots:
FWH & CNR Connector 19
AGP2.0 SLOT * 1 USB & FAN Connectors 20
PCI2.2 SLOT * 3 (PCI Slot 3 for Medion Option)
B Front Panel & Connectors 21 B
CNR1.2 SLOT * 1
ACPI Controller 22
L6719B CPU Power ( PWM )-VRM9.0 23
ERP BOM Function Description
IO Connectors 24
601-6507E-01S MS-6507E 100 With LAN.
601-6507E-020 MSI Option:L MSI Standard JUMPER SETTING 25
601-6507E-02S MS-6507E 100 Without LAN.
601-6507E-010 MSI Standard MSI Standard
History I 26
601-6507E-XXX
Medion SPEC. LAYOUT GUIDE
With CNR,STR. W/O ISA,LAN. 27-31
For Actebis: I/O with Shield.
A A
Title Rev
Micro-Star MS-6507E 1.0
Document Number
Cover Sheet
Last Revision Date:
Monday, April 15, 2002 Sheet 1 of 31
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
( 100/133MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
( 100/133MHz)
CONN 9.0 Socket (mPGA478-B)
( 400/533MHz) S calable Bus S calable Bus/2
AGP 4 X (66MHz) AGP
4X(1.5V) AGP 4X
(1.5V) MCH: Memory
AGP CONN
Controller HUB
( 5 93PINS/FCBGA) ( 200/266MHz)
DDR DIMM 1:2
( 66MHz X 4 ) H UB Interface
( 14.318MHz)
C Heceta Hardware SM Bus C
Monitor ICH4: I/O P CI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Lan /
(48MHz) RealTek RJ-45
8100BL Connector
( 3 3MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3
AC '97 Audio
FWH: Firmware HUB
Codec Line Out
SIO
T elephone In
MIC In
B Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
CD-ROM
Keyboard Serial (2) Drive CONN
A A
Title Rev
M i cro-Star MS-6507E 1.0
Document Number
Block Diagram
Last Revision Date:
Monday, April 15, 2002 Sheet 2 of 31
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Delivery Map
D D
A T X 12V POWER Supply
3.3V 5V 5VSB 12V
1A
VRM9.2 P rocessor Core
P rocessor Vtt
Power
Translator
ACPI IC 1.5V VREG M CH Core 1.5V
MCH Vtt
MCH AGP
C OP 1.8V VREG M C H H UB Interface 1.8V C
M C H Memory DDR 2.5V
POWER CONSUMPTION
3.3V
DUAL VCCP VCC_AGP VCC1_8 VCC3_DIMM VCC3 VCC5 VCC5_SB +12V -12V
FET DDR System Memory 2.5V CPU 69.0A 0 0 0 0 0 0 NOTE4 0
3.3V VREG MCH 2.4A NOTE1 0.2A 2.0A 0 0 0 0 0
ICH4 0 0 NOTE3 0 NOTE3 0 NOTE3 0 0
ICS950213 0 0 0 0 0 0 0 0 0
ALC201A 0 0 0 0 0 0 0 0
I CH2 Core 1.8V FWH -SST 0 0 0 0 0
W83627HF 0 0 0 0 0 0 0 0
I CH2 I/O 3.3V L6917BD 0 0 0 0 0 0 0
DIMM 0 0 0 NOTE2 0 NOTE2 0 0
I C H2 Resume 3.3V AGP 0 8.0A 0 0 6.0A 2.0A ? 1.0A 0
PCI 0 0 0 0 0 0 0 0
1.8V VREG I C H 2 Resume I/O 1.8V USB 0 0 0 0 0
USB HUB 0 0 0 0 0 0 0 0 0
5V TO 3.3V I CH2 RTC 3.3V FAN 0 0 0 0 0 0 0 0 0
RESISTOR TTL 0 0 0 0 0 0 0 0 0
ICH2 5V AMPLIFIER 0 0 0 0 0 0 0
OTHER 0 0 0 0 0 0
B B
FWH 3.3V
NOTE1 --- MCH
VCC_AGP = VCC1_5 (1.5A) + VCC_AGP (0.37A)
L P C Super I/O 3.3V
NOTE2 --- DIMM
S0 STATE --- 2.0A * 1 = 4.0A ---> V DM
_I M
S1/S3 STATE --- 200mA * 2 = 400mA ---> V DM
_I M
C L OCK GEN 3.3V V_DIMM -->400mA*2.5V/3.3V=303mA --> VCC3_S B
NOTE3 --- ICH4
Power S0 S1 S3/S4/S5
H A R D WARE AUDIO 3.3V 1.8V 132mA 99mA N/A
VCC_AGP 550mA 266mA N/A
VCC1_5SB 82mA 52mA 25mA
VCC3(I/O) 528mA 0.76mA N/A
P C I LAN 3.3V/2.5V VCC3_SB 167mA 1mA 0.8mA / N/A
VCC3_SB =
VCC1_8SB =
5 V D u a l For USB and K/B VCC5_SB = VCC3_SB + VCC1_8SB
A A
Title Rev
M i cro-Star MS-6507E
Document Number
Power Delivery Map
Last Revision Date:
Monday, April 15, 2002 Sheet 3 of 31
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH4
GPIO Pin Type Function
GPIO 0 I REQ#A FWH
GPIO 1 I REQ#5
GPIO Pin Type Function
GPIO 2 I I R Q E#
GPI 0 I ATA IDE 1 Detect
GPIO 3 I I R Q F#
GPI 1 I ATA IDE 2 Detect
GPIO 4 I I R Q G#
GPI 2 I R e s e rved
GPIO 5 I I R Q H#
C
GPI 3 I R e s e rved C
GPIO 6~7 I Not Implemented
GPIO 8 I SIO_PME#
GPIO 9~10 I Not Implemented DEVICE ICH INT Pin IDSEL CLOCK
GPIO 11 I External SMI
PCI Slo t 1 INTA# AD16 P C I CLK0
GPIO 12~13 I Not Implemented INTB#
INTC#
GPIO 14~15 I Not Implemented
INTD#
GPIO 16 O Non Connect
PCI Slo t 2 INTB# AD17 P C I CLK1
GPIO 17 O GNT#5
INTC#
GPIO 18~21 O Non Connect INTD#
INTA#
B GPIO 22 O/D Non Connect B
GPIO 23 O BIOS Protect PCI Slo t 3 INTC# AD18 P C I CLK2
INTD#
GPIO 24~27 I/O Non Connect
INTA#
GPIO 28 I/O LAN DISABLED (ICH4) INTB#
GPIO 29~47 I/O Non Connect
PCI Slo t 3 INTG# AD19 P C I CLK3
P C I Lan INTD#/INTF# AD29 LANPCLK
A A
Title Rev
M i cro-Star MS-6507E 1.0
Document Number
GPIO Spec.
Last Revision Date:
Monday, April 15, 2002 Sheet 4 of 31
5 4 3 2 1
8 7 6 5 4 3 2 1
CLOCK GENERATOR BLOCK
*Trace < 0.5"
Shut Source Termination Resistors Pull-Down Capacitors
U13 CPUCLK R221 49.9RST
FB13 30S/0805 VCC3V 39 41 CPU0 R227 27.4RST CPUCLK CPUCLK# R222 49.9RST CPUCLK C175 X_10p
VCC3 CPU_VDD CPUCLK0 40 CPUCLK {6}
CPU0# R228 27.4RST CPUCLK# MCHCLK R219 49.9RST
CPUCLK0# CPUCLK# {6}
CB148 CB196 CB151 CB152 CB168 MCHCLK# R223 49.9RST CPUCLK# C176 X_10p
104P 104P X_106P/0805 X_104P 104P 36 38 CPU1 R229 27.4RST MCHCLK MCHCLK {8}
CPU_GND CPUCLK1 37 CPU1# R230 27.4RST MCHCLK# MCHCLK C178 X_10p
CPUCLK1# MCHCLK# {8}
filtering from 10K~1M
46 Trace less 0.2" MCHCLK# C177 X_10p
D MREF_VDD 45 D
* Put GND copper under Clock Gen. CPUCLK2 44 RN57 8P4R-33 49.9ohm for 50ohm M/B impedance
CB171
connect to every GND pin 104P 43 CPUCLK2# 1 2 MCH_66
MREF_GND 3 4 MCH_66 {8}
* 40 mils Trace on Layer 4 ICH_66 2 1
32 31 5 6 AGPCLK
ICH_66 {13}
AGPCLK {15}
CLOCK STRAPPING RESISTORS AGPCLK 4 3 CN12
with GND copper around 3V66_VDD 3V66_0 30 7 8 ICH_66 6 5 X_8P4C-10P
CB150 3V66_1 28 FS0 R246 1K VCC3V MCH_66 8 7
it 104P 29 3V66_2 27 SEL48_2
3V66_GND 3V66_48/SEL66_48# FS1 R239 X_10K VCC3V
* put close to every power pin 6 FS2 R240 10K
* FS2/PCI0 7 FS3 PCICLK3
Trace Width 7mils. 9 7 8
PCI_VDD FS3/PCI1 8 SEL48_1 R252 33 PCICLK0 5 6 CN13
* CB149 SEL48_24#/PCI2 7 8 PCICLK3 {16}
PCICLK1 3 4 X_8P4C-10P
Same Group spacing 15mils 104P 5 10 FS4 5 6 PCICLK0 PCICLK2 1 2
* PCI_GND FS4/PCI3 11 RN63 3 PCICLK1
PCICLK0 {16} RN65
Different Group spacing 30mils 4 PCICLK1 {16}
18 PCI4 12 8P4R-33 1 2 PCICLK2 SEL48_1 1 2 VCC3V
* PCI_VDD PCI5 14 7 8 LAN_PCLK
PCICLK2 {16}
FS3 3 4
Differentical mode spacing 7mils on itself CB154 PCI6 15 RN64 5 SIO_PCLK
LAN_PCLK {17}
FS2 LAN_PCLK
6 SIO_PCLK {18} 5 6 2 1
104P 13 PCI7 16 8P4R-33 3 4 FWH_PCLK FS4 7 8 SIO_PCLK 4 3 CN14
PCI_GND PCI8 17 1 2 FWH_PCLK {19}
ICH_PCLK ICH_PCLK {12} FWH_PCLK 6 5 X_8P4C-10P
PCI9 8P4R-10K ICH_PCLK 8 7
VCC3 FB14 X_80_0805 VDDA3V 24
C181 48_VDD 22 FS0 R247 33 ICH_48
CP12 X_COPPER 103P FS0/48MHz 23 ICH_48 {13}
FS1 R241 33 SIO_48 SIO_48 {18} SEL48_2 R225 10K ICH_14 C174 10P
21 FS1/24_48MHz
48_GND SIO_48 C180 10P
2
CB153 CB157 C194 REF_VDD 48 MUL0 R232 33 ICH_14 ICH_48 C193 10P
MUL0/REF0 1 ICH_14 {13}
C 104P X_476P/0805 103P MUL1 MUL0 R220 10K MUL0=0 C
47 MUL1/REF1 MUL1=1
REF_GND MUL1 R248 X_10K Ioh=6*Iref
34 3 X1 C192 22P Voh=0.71V
C189 CORE_VDD X1
103P X1 14M-32pf-HC49S-D
33 4 X2 C187 22P used only for EMI issue
CORE_GND X2
{10,18,19,22} SMBCLK_ISO SMBCLK_ISO 26 35 R231 475RST Iref = 2.32mA Trace less 0.2"
SMBDATA_IS 25
O SCLK IREF
{10,18,19,22} SMBDATA_ISO SDATA 20 FS4 FS3 FS2 FS1 FS0 FSB (MHz)
R280 1K 19 RESET# 42 PWR_DN# R226 1K VCC3V
VCC3 VTT_GD# PWR_DN# 1 1 1 0 1 100 MHz
C
CY28349
R265 B Q27 R279
VCCP 1 1 1 1 1 133 MHz
220 2N3904S VCC3 VCC3 VCC3 VCC3
X_1K
E
R254 X_10K
C
VCC3
R255 Q24
{6} SKTOCC# B CB167 CB147 CB170 CB146 SMBCLK_ISO R233 4.7K VCC3
X_2N3904S 104P 104P 104P 104P SMBDATA_ISO R234 4.7K
X_220
E
SECONDARY IDE BLOCK
B FS4 FS3 FS2 FS1 FS0 CPU (MHz) PRIMARY IDE BLOCK B
1 1 1 0 1 100 MHz IDE2
IDE1 YJ220-CW-1 SDD[8..15] {13}
1 1 1 1 1 133 MHz YJ220-CB-1 HD_RST# R177 33 1 2
{22} HD_RST# HD_RST# R180 33 1 2 {13} SDD[0..7] SDD7 3 4 SDD8
{13} PDD[0..7] PDD7 3 4 PDD8 SDD6 5 6 SDD9
PDD6 5 6 PDD9 SDD5 7 8 SDD10
VCC_AGP PDD5 7 8 PDD10 SDD4 9 10 SDD11
PDD4 9 10 PDD11 SDD3 11 12 SDD12
BSEL0 {6} PDD3 11 12 PDD12 SDD2 13 14 SDD13
PDD2 13 14 PDD13 SDD1 15 16 SDD14
R147 PDD1 15 16 PDD14 SDD0 17 18 SDD15
1.5K R128 PDD0 17 18 PDD15 19
2.2K 19 PDD[8..15] {13} {13} SD_DREQ 21 22
A C FS1 21 22 23 24
{13} PD_DREQ 23 24 {13} SD_IOW# 25 26
R148 D10 {13} PD_IOW# 25 26 {13} SD_IOR# 27 28
{13} PD_IOR# {13} SD_IORDY
1K X_1N4148S 27 28 29 30
R129 {13} PD_IORDY 29 30 {13} SD_DACK# 31 32
{9,15} ST1 {13} PD_DACK# {12} IRQ15
2.2K {12} IRQ14 31 32 {13} SD_A1 33 34 SD_DET {19}
C
{13} PD_A1 33 34 PD_DET {19} {13} SD_A0 35 36 SD_A2 {13}
Q17 B {13} PD_A0 35 36 PD_A2 {13} {13} SD_CS#1 37 38 SD_CS#3 {13}
2N3904S {13} PD_CS#1 37 38 PD_CS#3 {13} {21} SD_LED 39 40
R130 {21} PD_LED 39 40 C100
E
X_8.2K C101 473P
473P R88 C108 R117
R92 C107 R118 4.7K X_220P 10K
4.7K X_220P 10K
A VCC5 VCC3 A
VCC5 VCC3
MSI MICRO-STAR INT'L CO.,LTD.
ATA100 IDE CONNECTORS *
*
*
Trace Width : 5mils
Trace Spacing : 7mils
Length(longest)-Length(shortest)<0.5"
Title
Clock Gen & ATA100 IDE Connectors
* Trace Length less than 5" Size Document Number Rev
1.0
MS-6507E
Date: Monday, April 15, 2002 Sheet 5 of 31
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK
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