Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6501
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1
Cover Sheet 1
MS-6501 ATX
Block Diagram 2
Clock Synthesizer 3 Version
PGA462 Socket A CPU0/CPU1 4,5,6,7 0C
AMD 762--------North Bridge 8,9,10,11,12
DDR DIMM-184 13,14 Last Update 11/12/2001
AGP 4X SLOT 15
PCI Connectors 16,17,18,19
CPU:
Dual AMD Socket-462 Processors
AMD 768--------South Bridge 20,21
LPC SuperI/O 22
ATA66/100 Connectors 23
Parallel / Serial Port 24
System Chipset:
Keyboard & Mouse 25
AMD 762(North Bridge)
AMD 768 (South Bridge)
BIOS & FANs 26
Front Panel 27
A A
USB Conector 28
Expansion Slots:
AC'97 Codec 29
AGP-Pro SLOT * 1
Audio/Game Port 30
PCI2.2 PCI/64/66 SLOT * 2
DDR Regulator & STR LDO 31
PCI2.2 PCI/32/33 SLOT * 3
LAN 32
MS-3 33
On Board:
VRM 34
LAN 82559ER
DDR Terminator 35
AC97 Codec
IGD4 PCI Strappings 36
PC 2 PC
OPUS PCI Strappings 37
Bypass Capacitors 38
Mounting Hole 39
MICRO-STAR
Power/Clock Map 40,41 Title
Cover Sheet
Size Document Number Rev
Custom MS-6501 0C
1
Date: Tuesday, November 20, 2001 Sheet 1 of 41
1
K7 462-Pin
Socket
K7 462-Pin
Socket
Block Diagram
VRM Clock
Processor Processor
AMD SYSTEM BUS
AMD SYSTEM BUS
VTT 1.25V
Regulator
4
AGP PRO Register
2X/4X AMD762
DDR
North Bridge DIMM
Modules
PCI Conn 1
PCI Conn 2
PCI CNTRL
PCI ADDR/DATA
A A
UltraDMA
IDE Primary 33/66/100
IDE Secondary AMD 768
South
USB Port 1 USB Bridge
PCI ADDR/DATA
PCI Conn 3
PCI Conn 4
PCI Conn 5
PCI CNTRL
USB Port 2
USB Port 3
INTEL
USB Port 4 PC 2 PC 82559ER
LPC LAN
AC'97 Bus
Link Super I/O
Onboard BIOS
AC'97 Codec
10/100Mbps
Conn.
Keyboard Floopy Parallel Serial Game Conn
Mouse MICRO-STAR
Title
Block Diagram
Size Document Number Rev
Custom MS-6501 0C
Date: Tuesday, November 20, 2001 Sheet 2 of 41
1
5 4 3 2 1
* 25 mils Trace on Layer 6
with GND copper around it
VCC3
* Put close to every power pin
Clock Synthesizer
10u
FB16
D D
EC44
80-0805
330p C337
330p C339
0.01u C538
0.01u C533
0.01u C529
0.01u C537
0.01u C373
0.01u C372
FB15 +
80-0805
C376 C371 +
C354 EC42 C358
0.01u 0.01u 0.01u 330p
10u
VCC3
R302 X_10
CPUCLK2 <8>
34
48
45
15
18
22
2
4
6
8
9
U24
RN77
VDDPCI1
VDDPCI2
VDD
VDDREF
VDDSD
VDDAGP
VDD48
R435 10 C564 10p
10K
Y3 4 42 CPUCLKT2
X1 CPUCLKT2 CPUCLKC2 RN72 10
5 X2 CPUCLKC2 43 Length = X" (5 mil trace / 20 mil clearance)
1
3
5
7
39 CPUCLKT1 1 2
CPUCLKT1 CPUCLK1 <6>
14M-16pf-HC49S-D 32 40 CPUCLKC1 3 4
<21> PCISTP- PCI_STOP_L CPUCLKC1 CPUCLK-1 <6>
36 CPUCLKT0 5 6 Length = X" - 1" (20/5/5/5/20)
CPUCLKT0 CPUCLK0 <4>
R335 22-REV 31 37 CPUCLKC0 7 8
<21,33> CPUSTOP- CPU_STOP_L CPUCLKC0 CPUCLK-0 <4>
R340 22-REV 30 46
<27,33> FP_RST- PD_L SDRAM_OUT
17 PCICLK6 RN75 1 2 22 Length = X"
PCICLK6 LANCLK <32>
29 16 PCICLK5 3 4 (5 mil trace / 20 mil clearance)
SPREAD_L PCICLK5 PCLK5 <19>
14 PCICLK4 5 6
PCICLK4 PCLK4 <18>
13 PCICLK3 7 8 Length = X" - 2.5" (5 mil trace / 20 mil clearance)
PCICLK3 PCLK3 <18>
C 28 11 PCICLK2 C
<33,36> 100/133- FS2 PCICLK2 PCLK2 <26>
2 10 R671 22
R295 22 FS1 PCICLK1
<21> OSC 1 FS0 PCICLK0 8
7 PCICLK_FB Length = X" (5 mil trace / 20 mil clearance)
R616 22 PCICLK_F0
24 24MHZ/48MHZ#
<22> SIO_CLK24 AGP1 R333 27
AGP1 20 GCLK1 <15>
35 19 AGP0 R332 27 Length = X" (5 mil trace / 20 mil clearance)
GCLK0 <11>
2
4
6
8
RSVD2 AGP0
44 RSVD1 Length = X" - 4.5" (5 mil trace / 20 mil clearance)
RN68 23 USB0 R336 22
USB0 USBCLK <21>
C326
10p 10K
26
GND
GND
GND
GND
GND
GND
GND
GND
GND
SCLK SMBCLK <13,14,21,22,33>
SDATA 27 SMBDATA <13,14,21,22,33>
1
3
5
7
12 ICS 9248-153
21
25
33
38
41
47
3
6
R298
JFSB1 1M-REV
1 1
2 2
3 C346 22p-REV
3
*Put GND copper under Clock Gen. CPUCLKT2 2 1 PCICLK_FB R654 39
SIO_PCLK <22>
C336 C335
D1x3-BK connect to every GND pin R655 39
SBCLK <21>
22p 22p CN15 22p
JP2(1-2) NOPOP NOPOP CPUCLKC1 7 8
JC-D2-RD CPUCLKT1 5 6
NOPOP CPUCLKC0 3 4
CPUCLKT0 1 2
B B
SIO_PCLK C845 10p
NOPOP
WIDTH/SPACE LENGTH CPU SBCLK C846 10p
FS2 FS1 FS0 PCI AGP NOPOP
CPUCLK0&CPUCLK0#: 5/20 5 FOR DIFF. PAIR X-1 INCH SDRAM
CPUCLK1&CPUCLK1#: 5/20 5 FOR DIFF. PAIR X-1 INCH 0 0 0 133.3 33.3 66.7 CN16 10p
PCICLK6 7 8
CPUCLK2&GCLK0 5/20 X PCICLK5 5 6
0 0 1 95.0 31.67 63.33 PCICLK4 3 4
GCLK1 5/20 X-4.5 PCICLK3 1 2
NOPOP
NBCLK&SBCLK 5/20 X 0 1 0 100.99 33.66 67.33
PCICLK GROUP 5/20 X-2.5
0 1 1 115.0 38.33 76.67
AGP1 C369 1 2 22p
1 0 0 100.7 33.57 67.13 AGP0 C367 1 2 22p
USB0 C374 10p
* X MEANS THE SHORTEST LENGTH FOR MAINTAIN 1 0 1 103.0 34.33 66.6 NOPOP
PROPAGATION DELAY
1 1 0 105.0 35.00 60.0
* CPUCLK1'S TERMINATION CKT MUST BE PLACED
NEAR TO NB
1 1 1 110.0 36.67 66.6 Close to clock generator
A A
MICRO-STAR
Title
Clock Synthesizer
Size Document Number Rev
Custom MS-6501 0C
Date: Tuesday, November 20, 2001 Sheet 3 of 41
5 4 3 2 1
A B C D E
VCORE
CPU1A **All CPU interface are 2.5V tolerant**
P0_SDATA-0 AA35 AE1 A20M- A20M- <6,21> P0_DBREQ- R313 510
<8> P0_SDATA-[0..63] P0_SDATA-1 SDATA0 A20M FERR_P0
W37 SDATA1 FERR AG1
P0_SDATA-2 CPUINIT- FERR_P0 <21>
W35 SDATA2 INIT AJ3
P0_SDATA-3 INTR CPUINIT- <6,21>
Y35 SDATA3 INTR AL1
P0_SDATA-4 U35 AJ1 IGNNE- INTR <6,21> P0_PLLTEST- R305 510
P0_SDATA-5 SDATA4 IGNNE NMI IGNNE- <6,21>
U33 SDATA5 NMI AN3
P0_SDATA-6 S37 AG3 CPURST- NMI <6,21>
P0_SDATA-7 SDATA6 RESET SMI- CPURST- <6,21>
S33 SDATA7 SMI AN5
P0_SDATA-8 STPCLK- SMI- <6,21>
4 AA33 SDATA8 STPCLK AC1 4
P0_SDATA-9 AE37 STPCLK- <6,21> C351 RN80
P0_SDATA-10 SDATA9 4700p-REV P0_CPU_TCK
AC33 SDATA10 PWROK AE3 CPU_PG <6,27> 2 1
P0_SDATA-11 AC37 P0_CPU_TMS 4 3
P0_SDATA-12 SDATA11 R315 100 P0_CPU_TRST-
Y37 SDATA12 6 5
P0_SDATA-13 AA37 N1 APICCLK P0_CPU_TDI 8 7
SDATA13 PICCLK APICCLK <6,21>
P0_SDATA-14 AC35 N3 APICD0-
SDATA14 PICD0/BYPASSCLK APICD0- <6,21>
P0_SDATA-15 S35 N5 APICD1-
SDATA15 PICD1/BYPASSCLK APICD1- <6,21>
P0_SDATA-16 Q37 510
P0_SDATA-17 SDATA16 P0_COREFB-
Q35 SDATA17 COREFB- AG13 P0_COREFB- <34>
P0_SDATA-18 N37 AG11 P0_COREFB
SDATA18 COREFB+ P0_COREFB <34>
P0_SDATA-19 J33
P0_SDATA-20 SDATA19 CPUCLK0_R
G33 SDATA20 CLKIN AN17
P0_SDATA-21 G37 AL17 CPUCLK-0_R
P0_SDATA-22 SDATA21 CLKIN R293 R285
E37 SDATA22
P0_SDATA-23 G35 AN19
P0_SDATA-24 SDATA23 RSTCLK 0 0
Q33 SDATA24 RSTCLK AL19
P0_SDATA-25 N33
P0_SDATA-26 SDATA25 P0_CLKOUT AMD use 100ohm
L33 SDATA26 K7CLKOUT AL21
P0_SDATA-27 N35 AN21 P0_CLKOUT-
P0_SDATA-28 SDATA27 K7CLKOUT VCORE
L37 SDATA28
P0_SDATA-29 J37 The farest VCORE and GND
P0_SDATA-30 SDATA29
A37 SDATA30 ANALOG AJ13
P0_SDATA-31 E35
P0_SDATA-32 SDATA31 P0_VREFMODE
E31 SDATA32 SYSVREFMODE AA5
P0_SDATA-33 E29 W5 P0_VREF_SYS
P0_SDATA-34 SDATA33 VREF_SYS
A27 SDATA34
P0_SDATA-35 A25 AC5 P0_ZN
P0_SDATA-36 SDATA35 ZN P0_ZP VCORE
E21 SDATA36 ZP AE5
P0_SDATA-37 C23 RN63
P0_SDATA-38 SDATA37 P0_PLLBP-
3 C27 SDATA38 PLLBYPASS AJ25 8 7 3
P0_SDATA-39 A23 AN15 6 5
P0_SDATA-40 SDATA39 PLLBYPASSCLK
A35 SDATA40 PLLBYPASSCLK AL15 4 3
P0_SDATA-41 C35 2 1
P0_SDATA-42 SDATA41 P0_PLLMON1
C33 SDATA42 PLLMON1 AN13
P0_SDATA-43 C31 AL13 P0_PLLMON2 100
P0_SDATA-44 SDATA43 PLLMON2 P0_PLLTEST-
A29 SDATA44 PLLTEST AC3
P0_SDATA-45 C29 VCORE VCORE
P0_SDATA-46 SDATA45 RN76 VCORE
E23 SDATA46
P0_SDATA-47 C25 S1 P0_SCANCLK1 INTR 7 8
P0_SDATA-48 SDATA47 SCANCLK1 P0_SCANCLK2 CPUINIT-
E17 SDATA48 SCANCLK2 S5 5 6
P0_SDATA-49 E13 S3 P0_SINTVAL NMI 3 4 R280 for internal VREFSYS R283
P0_SDATA-50 SDATA49 SCANINTEVAL P0_SSHIFTEN SMI- 1K-REV 100
E11 SDATA50 SCANSHIFTEN Q5 1 2
P0_SDATA-51 C15 P0_VREFMODE 0.5 * VCORE
P0_SDATA-52 SDATA51 P0_CPU_DBRDY 680 P0_VREF_SYS
E9 SDATA52 DBRDY AA1
P0_SDATA-53 A13 AA3 P0_DBREQ- R282
P0_SDATA-54 SDATA53 DBREQ P0_FLUSH- RN66 270
C9 SDATA54 FLUSH AL3
P0_SDATA-55 A9 IGNNE- 1 2 C321 C320 C319 R281
P0_SDATA-56 SDATA55 P0_CPU_TCK CPURST- 100
C21 SDATA56 TCK Q1 3 4
P0_SDATA-57 A21 U1 P0_CPU_TDI A20M- 5 6 39p 1000p
P0_SDATA-58 SDATA57 TDI P0_CPU_TDO STPCLK- 0.047u
E19 SDATA58 TDO U5 7 8 VREFMODE=Low=No voltage scaling
P0_SDATA-59 C19 Q3 P0_CPU_TMS
P0_SDATA-60 SDATA59 TMS P0_CPU_TRST- 680
C17 SDATA60 TRST U3
P0_SDATA-61 A11
P0_SDATA-62 SDATA61 P0_PLLMON1 R286 56
A17 SDATA62
P0_SDATA-63 A15 L1 P0_VID0 P0_PLLMON2 R284 56
SDATA63 VID0 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo