Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6534
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8 7 6 5 4 3 2 1
Cover Sheet
Block Diagram
1
2
MS-6534 Version
1.0A
INTEL (R) Brookdale Chipset
GPIO Spec. 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Clock CY28323 & ATA100 IDE CONNECTORS 4
mPGA478-B INTEL CPU Sockets 5-6
CPU:
INTEL Brookdale MCH -- North Bridge 7-8
Willamette/Northwood mPGA-478B Processor
INTEL ICH2 -- South Bridge 9 - 10
LPC I/O W83627HF 11 System Brookdale Chipset:
PCI AUDIO-CMI8738 12 INTEL MCH (North Bridge) +
AC'97 Codec 13 INTEL ICH2 (South Bridge)
C On Board Chipset: C
Audio Amp TL072 & GAME 14
BIOS -- FWH
FWH -- BIOS & CNR RISER 15
LPC Super I/O -- W83627HF
SDR DIMM-168PIN DIMM1,2 16
Clock Generation -- CY28323
AGP 4X SLOT (1.5V) 17
(OPTION) PCI SOUND -- C-MEDIA CMI8738
PCI SLOT 1 & 2 & 3 18
Front Panel & Connectors 19
Expansion Slots:
USB & FAN Connectors 20
B
AGP2.0 SLOT * 1 B
AUDIO 4/6 CHANNEL CONTROL 21 PCI2.2 SLOT * 3
Votlage Regulator 22 CNR SLOT * 1
HIP6301 CPU Power ( PWM )-VRM9.X 23
Standard: 2 Channel S/W Audio-Realtek ALC201A
IO Connectors 24 Option A: 6 Channel H/W Audio-C media 8738
History 25 Option B: 4 Channel S/W Audio-Sigmatel 9708
MANUAL 26
POWER DELIVERY MAP 27
A A
Title Rev
M i c ro-Star MS-6534 10A
Document Number
Cover Sheet
Last Revision Date:
Friday, August 10, 2001 Sheet 1 of 27
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.X Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
AGP 4 X (66MHz) AGP
4X(1.5V) AGP 4X
(1.5V) MCH: Memory
AGP CONN
Controller HUB
( 5 93PINS/FCBGA) (133MHz)
DIMM 1:2
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C C
ICH2: I/O PCI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Audio /
(48MHz) C-MEDIA SPDIF/OUT
CMI8738
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3 CNR Riser
AC '97 Audio
FWH: Firmware HUB AMP
Codec
SIO
Line Out
Telephone In
MIC In
B
Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
CD-ROM
Keyboard Serial (2) Drive CONN
Game (1)
A A
Title Rev
M i c ro-Star MS-6534 10A
Document Number
Block Diagram
Last Revision Date:
Friday, August 10, 2001 Sheet 2 of 27
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH2 FWH
GPIO Pin Type Function Power GPIO Pin Type Function
* GPIO 0 I Non Connect(REQA#) Main GPI 0 I ATA IDE 1 Detect
GPIO 1 I Non Connect(REQ5#) Main GPI 1 I ATA IDE 2 Detect
GPIO 2 I INTE# Main GPI 2 I Reserved
GPIO 3~5 I Non Connect(INT[F:H]#) Main GPI 3 I Reserved
GPIO 6 I Onboard AC97 Enabled#/Disabled Main
* GPIO 7 I H/W Monitor auto detect Main
C C
GPIO 8 I LAN_WAKE# Resume
GPIO 9 Not Implemented
GPIO 10 Not Implemented DEVICE ICH INT Pin IDSEL
* GPIO 11 I Non Connect(SMB_ALERT) Resume
PCI Slot 1 INTA# AD16
GPIO 12 I External SMI Resume INTB#
INTC#
GPIO 13 I LPC PME Resume
INTD#
GPIO 14~15 Not Implemented
PCI Slot 2 INTB# AD17
GPIO 16 O Non Connect(GNTA#) Main
INTC#
GPIO 17 O Non Connect(GNT5#) Main INTD#
INTA#
B
GPIO 18 O Non Connect Main B
GPIO 19 O Non Connect Main PCI Slot 3 INTC# AD18
INTD#
GPIO 20 O Non Connect Main
INTA#
GPIO 21 O Non Connect Main INTB#
GPIO 22 OD Non Connect Main Combo INTG# AD19
GPIO 23 O BIOS Locked/Unlocked Main
PCI Audio INTF# AD25
GPIO 24 I/O Non Connect Resume
GPIO 25 I/O Non Connect Resume
GPIO 26 Not Implemented
GPIO 27 I/O Non Connect Resume
A A
GPIO 28 I/O Non Connect Resume
GPIO 29~31 Not Implemented
Title Rev
M i c ro-Star MS-6534 10A
*: Reserve For Auto Detect
Document Number
GPIO Spec.
Last Revision Date:
Friday, August 10, 2001 Sheet 3 of 27
5 4 3 2 1
8 7 6 5 4 3 2 1
for good filtering from 10K~1M
*Trace less 0.5"
CP3
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
X_COPPER CPUCLK R3 49.9
U1 CPUCLK# R4 49.9
FB1 X_600 39 41 R5 33 CPUCLK MCHCLK R6 49.9
VCC3 CPU_VDD CPU0 CPUCLK 5
40 R7 33 CPUCLK# MCHCLK# R8 49.9
+
CB1 CPU0# CPUCLK# 5
Rubycon CT1 CB418 CB2
0.1u 1u 0.1u 36 38 R10 33 MCHCLK
CPU_GND CPU1 37 R12 33 MCHCLK 7
MCHCLK# MCHCLK# 7
D 10u CPU1# CN16 D
46 MCH_66 1 2
MREF_VDD 45 C_STP ICH_66 3 4
CB3 3VMREF/CPU_STP# 44 P_STP
Trace less 0.2" AGPCLK 5 6
0.1u 3VMREF#/PCI_STP#
43 49.9ohm for 50ohm M/B impedance 7 8
for good filtering from 10K~1M MREF_GND
32 31 1 2 MCH_66 MCH_66 7 X_10p
CP4 3V66_VDD 3V66_0 30 RN1 3 4 ICH_66 CN17
3V66_1 ICH_66 10
CB4 28 33 5 6 AGPCLK X_10p
R15 0.1u 29
3V66_GND
3V66_2
3V66_3
27 7 8 C517 10p AGPCLK 17 CLOCK STRAPPING RESISTORS SIO_PCLK 8 7
X_0 3V66_3 FWH_PCLK 6 5
X_COPPER 6 FS2 MODE 1 2 SIO_PCLK SIO_PCLK 11 ICH_PCLK 4 3
FB2 X_600 VCC3V 9 FS2/PCI_F0 7 FS3 RN48 3 4 FWH_PCLK FS4 R16 10K VCC3V 2 1
VCC3 PCI_VDD FS3/PCI_F1 8 FWH_PCLK 15
MODE FS2 5 6 ICH_PCLK FS3 R17 10K VCC3V
+
MODE/PCI_F2 ICH_PCLK 9
CB5 Rubycon CT2 CB419 CB6 33 7 8 CN18
0.1u 1u 0.1u 5 10 FS4 VCC3 FS1 R18 X_10K VCC3V 10p
PCI_GND FS4/PCI0 11 R555 33 PCICLK4 R20 10K PCICLK0 7 8
10u PCI1 PCICLK4 12
18 12 PCICLK1 5 6
PCI_VDD PCI2 14 7 8 PCICLK0 PCICLK2 3 4
CB7 PCI3 15 RN3 5 6 PCICLK0 18
PCICLK1 PCICLK1 18 FS0 R22 10K VCC3V PCICLK5 1 2
0.1u PCI4 33 PCICLK2 C621 C622 R23 X_10K
13 16 3 4 PCICLK2 18
PCI_GND PCI5 17 1 2 PCICLK5 PCICLK4
*Put GND copper under Clock Gen. PCI6 PCICLK5 18 X_104P
FS2 R24 10K C519 X_10p
connect to every GND pin 24 X_104P R693 X_10K VCC3V
48_VDD 22 FS0 R26 33 ICH_48
* 40 mils Trace on Layer 4 FS0/48MHz ICH_48 10
CB8 23 FS1 R27 33 SIO_48 MODE R28 X_10K
with GND copper around it 0.1u 21 FS1/24_48MHz SIO_48 11 for 28324 AUDIO_14 C520 22p
48_GND
* put close to every power pin 2 VCC3
C C
REF_VDD 48 MUL0 R557 33 ICH_14 MUL0 R30 X_10K VCC3V ICH_48 C18 10p
* Trace Width 7mils. CB9 MUL0/REF0
1 MUL1 R558 33 AUDIO_14 ICH_14 10 R31 10K SIO_48 C19 10p
MUL1/REF1 AUDIO_14 12,13
0.1u 47
* Same Group spacing 15mils REF_GND MUL1 R32 10K VCC3V
34 3 C21 22p C607 C608 R33 X_10K
* Different Group spacing 30mils CORE_VDD X1 32pF
100p
CB10 X1 14M-32pf-HC49S-D
* Different mode spacing 7mils on itself 0.1u 33 4 C23 22p 0.01u CRST# R34 10K VCC3V ICH_14 C22 10p
CORE_GND X2
10,11,15,16 SMBCLK SMBCLK 26 35 R35 475
SCLK IREF
VCC3 R559 10K 10,11,15,16 SMBDATA SMBDATA 25
SDATA
SMBCLK R36 4.7K
VCC3 used only for EMI issue
20 CRST# SMBDATA R39 4.7K
R560 VTT_GD# 19 RST# 42 R38 4.7K VCC3V
1 2 Q53 VTT_GD# PWR_DN# VCC3V Trace less 0.2"
VCCP NPN-3904LT1-S-SOT23 X_1K CYP-CY28323 C_STP R13 X_1K VCC3V
220 R787 ICS950208 P_STP R14 X_1K
+12V CY28323
R788
100K Q88
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
R789 C636
NPN-3904LT1-S-SOT23
ATA100 IDE CONNECTORS
10K 1u-0805 R41 X_4.7K IDE1 R42 X_4.7K IDE2
D2x20-1:21-BL-ZBT D2x20-1:21-WH-SBT
HD_RST# R43 33 1 2 HD_RST# R44 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
B 10 PDD[0..7] PDD6 PDD9 PDD[8..15] 10 10 SDD[0..7] SDD[8..15] 10 B
5 6 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
10 PD_DREQ 21 22 10 SD_DREQ 21 22
10 PD_IOW# 23 24 10 SD_IOW# 23 24
10 PD_IOR# 25 26 10 SD_IOR# 25 26
27 28 R45 470 27 28 R46 470
10 PD_IORDY 29 30 10 SD_IORDY 29 30
10 PD_DACK# 10 SD_DACK#
9 IRQ14 31 32 9 IRQ15 31 32
10 PD_A1 33 34 PD_DET 15 10 SD_A1 33 34 SD_DET 15
10 PD_A0 35 36 PD_A2 10 10 SD_A0 35 36 SD_A2 10
10 PD_CS#1 37 38 PD_CS#3 10 10 SD_CS#1 37 38 SD_CS#3 10
19 PD_LED 39 40 19 SD_LED 39 40
C24 R53 C25 C26 R56 C27
VCC5 R562 8.2K 220p 10K X_4700p VCC5 R563 8.2K 220p 10K X_4700p
VCC3 VCC3
A RESET BLOCK A
R55 1K VCC5
R57 330 VCC3 R58 330 VCC3 Title Rev
9 PCIRST#
PCIRST# 1 2
PCIRST#1 7,11,12,15
PCIRST# 3 4
PCIRST#2 17,18
PCIRST# 9 8 HD_RST# M i c ro-Star MS-6534 10A
U2A U2B U2D Document Number
R757 DM7407-SOIC14 C521 DM7407-SOIC14 DM7407-SOIC14
Clock CY28323/4 & ATA100 IDE
10K (VCC5_SB) (VCC5_SB) (VCC5_SB)
X_10P Last Revision Date:
Friday, August 10, 2001 Sheet 4 of 27
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCPS+ 23 VCCP
7 HA#[3..31] VCCPS- 23
R62
2/3*Vccp 49.9
VID[0..4] 11,23
GTLREF1
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
HA#7
HA#6
HA#5
HA#4
HA#3
HA#8
VID2
VID0
VID4
VID3
VID1
C28 C29 C30 R63
220p 220p 1u 100
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
L2
L3
L6
U3A
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
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