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8 7 6 5 4 3 2 1
Cover Sheet 1
Last Schematic Update Date:
Block Diagram 2
MAIN CLOCK GEN & IDE CONNECTOR 3 11/06/2002
D
mPGA478-B INTEL CPU Sockets 4-5 D
INTEL Brookdale-G /GL GMCH
DDR SLOT
6-8
9
MS-6557
STD:
VERSION:2.1A
DDR TERMINATOR 10 INTEL 845G (B01-0845G15-I06)+ ICH4 + Kinnereth-R(B06-562EZ05-I06)
INTEL ICH4 11 - 12 OPTION A:
INTEL 845G (B01-0845G15-I06)+ ICH4 + KENAI32(B06-8254005-I06)
CH7009 & DVI + TV OUT 13 - 14
Willamette/Northwood 478pin mPGA-B Processor Schematics
PCI SLOT / FWH 15 CPU:
USB PORT 1 2 3 16 Willamette/Northwood mPGA-478B Processor
LPC I/O(SMsC LPC47M133) 17
System Chipset:
C
COM & LPT & FDD & FAN 18 C
KB / MS CONNECTOR / POV3 19 INTEL 845G (North Bridge) + ICH4 (South Bridge)
AC'97 CODEC ADI1981A / ALC650 + SPDIF 20
AUDIO CONNECTORS
On Board Chip:
21
LPC Super I/O -- SMsC LPC47M133
VGA CONNECTOR 22
BIOS -- FWH
VRM 9.0 23 AC' 97 CODEC -- ADI1981A / 1981B / ALC650
ACPI CONTROLLER W83302 MS-5 24 CLOCK GENERATION -- ICS 950201AF
LAN -- INTEL Kenai 1000 / Kinnereth-R
LAN Kinnnereth-R 10/100 or Kenai1000 25
DVO -- CH7009 DV+ TV-OUT
LAN Kinnnereth-R 10/100 or Kenai1000 Connector 26 1394 -- NEC uPD72874(Optional)
ATX Connector 27
B B
2-PORT IEEE1394 - NEC_uPD72874 28
Decoupling Capacitor 29
Expansion Slots:
GPIO setting 30
PCI2.2 SLOT* 1 ( RISER CARD PCI*2 )
HISTORY 1 31
HISTORY 2 32
THE RED PAGES ARE MSI BOM NOT
A FOR IBM SPEC A
MICRO-STAR INT'L CO.,LTD.
Title
COVER PAGE
Size Document Number Rev
C MS-6557 2.1A
Date: Thursday, November 28, 2002 Sheet 1 of 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System Block Diagram
D D
SOCKET-478
Host
Simultaneous Bus
display
SSTL-2 Termination
VGA
CONNECTOR
DDR SDRAM (Only for DDR)
INTEL
TMDS LCD
DVI-A
110MHz 845G DIMM 1 DIMM 2 Rtt
AV & TV-OUT CH7009
S-VIDEO
C C
FRONT
Support 6 PCI Devices HyperZip
33MHz 512 MB REAR
IEEE PCI
1394 SLOT Audio Codec Audio port
AC'97 ADI1981A /
1 IDE
ALC650
ICH4
FRONT
USB2.0
SPDIF
REAR
USB 0 USB 2 USB 4
B B
USB 1 USB 3 USB 5
FWH
IDE 1 IDE 2 LPC Bus
REAR FRONT PORT
PORT
LAN Kinnnereth-R 10/100
or Kenai 1000
PS/2
KEYBOARD
RJ45 PS/2 LPC Super
MOUSE
I/O
FAN ON/OFF
CONTROL SMsC47M133
FAN1 FAN2
A A
LM86
GPIOs COM2 COM1 PARALLEL FLOPPY
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
Custom MS-6557 2.1A
Date: Thursday, November 28, 2002 Sheet 2 of 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Trace less 0.2"
CLOCK GENERATOR BLOCK *Trace < 0.5" 49.9ohm for 50ohm M/B impedance
CLOCK STRAPPING RESISTORS
CPUCLK0 R187 49.9RST
CP67 X_COPPER CPUCLK-0 R186 49.9RST
U34 FS1 R813 1.5K-0603 VDDA3V
FB16 X_80L-0805 CLK_VCC3 50 52 CPU0 R808 27.4RST CPUCLK0 MCHCLK R189 49.9RST
VCC3 VDDCPU CPUCLK0 CPUCLK0 (4)
46 51 CPU0# R810 27.4RST CPUCLK-0 MCHCLK# R188 49.9RST
VDDCPU CPUCLK0# CPUCLK-0 (4) BSEL0 (4,6)
C465 C466 49 CPU1 R814 27.4RST MCHCLK
CPUCLK1 MCHCLK (6)
0.1u-0603 10u-1206 C467 48 CPU1# R815 27.4RST MCHCLK# ITPCLK R1385 49.9RST
CPUCLK1# MCHCLK# (6)
47 45 R1386 27.4RST ITPCLK ITPCLK# R1387 49.9RST
GND CPUCLK2 ITPCLK (4)
D filtering from 10K~1M 0.1u-0603 44 R1388 27.4RST ITPCLK# FS2 FS1 FS0 CPU (MHz) D
CPUCLK2# ITPCLK# (4)
19 0 0 1 100 MHz CPUCLK0 C185 X_10p-0603
VDD3V66 3V66_0 R819 33-0603 MCH_66
* Put GND copper under Clock Gen. C468 3V66_0 33
3V66_1 R820 33-0603 ICH_66
MCH_66 (6)
CPUCLK-0 C186 X_10p-0603
3V66_1 35 ICH_66 (12) 0 1 1 133 MHz
connect to every GND pin 20 21
0.1u-0603 32 GND 3V66_2
* 40 mils Trace on Layer 4 VDD3V66 3V66_3 22
MCHCLK C103 X_10p-0603
3V66_4 23
with GND copper around C469 24
3V66_5 MCHCLK# C102 X_10p-0603
* put close to every power pin
it 0.1u-0603
31 GND
RN135 LAN_PCLK SMBCLK_ISO R839 4.7K-0603
Trace Width 7mils. 8 VDDPCI PCICLK_F0 5
33-8P4R
7 8
PCICLK1
LAN_PCLK (25) VCC3
PCICLK_F1 6 5 6 PCICLK1 (15)
* Same Group spacing 15mils C472 7 3 4 PCICLK2
PCICLK_F2 PCICLK2 (15)
9 10 1 2 POV_CLK SMBDATA_ISO R841 4.7K-0603
GND PCICLK0 POV_CLK (19)
* Different Group spacing 30mils 0.1u-0603 11 RN76 7 8 FWH_PCLK
PCICLK1 FWH_PCLK (15)
12 33-8P4R 5 6 ICH_PCLK CN4
PCICLK2 ICH_PCLK (11)
* Differentical mode spacing 7mils on itself 14 13 3 4 SIO_PCLK POV_CLK 1 2 X_10p-8P4C
VDDPCI PCICLK3 SIO_PCLK (17)
16 1 2 PCICLK2 3 4
C473 PCICLK4 REF_14 R1358 X_33-0603 ICH_14 PCICLK1
* CP68 X_COPPER PCICLK5 17
R1359 X_33-0603 SIO_14 LAN_PCLK
5 6
15 GND PCICLK6 18 7 8
0.1u-0603 R1374 X_33-0603 ADO_14M
FB17 X_80L-0805 VDDA3V 1 56 R826 33-0603 REF_14
VCC3 VDDREF REF CN3 1 2 X_10p-8P4C
C470 C471 C474 2 CLK_X1 C478 22p-0603 SIO_PCLK 3 4
0.1u-0603 10u-1206 X1 ICH_PCLK
4 GND 5 6
0.01u-0603 3 X1 14M-32pf-HC49S-D FWH_PCLK 7 8
for good filtering from 10K~1M X2 CLK_X2 32pF C481 22p-0603 U35
37 REF_14 1
C CP86 X_COPPER VDD48 R829 33-0603 ICH_48 REF ZD_CLK1 MCH_66 C580 X_10p-0603 C
48MHz_USB 39 ICH_48 (12) VCC3 6 VDD CLK1 3
C476 38 R831 33-0603 DOT_CLK 2 ZD_CLK2
48MHz_DOT DOT_CLK (6) CLK2
36 C642 5 ZD_CLK3 ICH_66 C581 X_10p-0603
R827 VCC3VA 0.01u-0603 GND 0.01u-0603 CLK3 ZD_CLK4
VCC3 4 GND CLK4 7
X_10-0603 26 42 IREF R840 475RST 8
VDDA IREF Iref = 2.32mA CLKOUT ICH_48 C479 X_10p-0603
C475 C480 41 CY2305SC-1H
10u-0805 GND SIO_14 C482 X_10p-0603
27 GND
I12-23S0502-C23
0.01u-0603 R809 X_1K-0603 C671 10p-0603
CLK_VCC3 53 43 R812 10K-0603 VDDA3V VDI_CLK C484 X_10p-0603
R1258 CPU_STP# MULTSEL0 R807 1K-0603
34 PCI_STP# FS0 54
1K-0603 25 55 FS1 ICH_14 C485 X_10p-0603
R843 10K-0603 PD# FS1 R811 1K-0603
VCC3 FS2 40
ZD_CLK1 R1182 33-0603 ADO_14M DOT_CLK C486 X_10p-0603
ADO_14M (20)
R845 30 SMBCLK_ISO
SCLK SMBCLK_ISO (19,24)
Q33 28 29 SMBDATA_ISO ZD_CLK3 R837 33-0603 ICH_14 ADO_14M C627 X_10p-0603
VCCP VTT_PWRGD# SDATA SMBDATA_ISO (19,24) ICH_14 (12)
2N3904S ZD_CLK4 R1259 33-0603 SIO_14
SIO_14 (17)
10K-0603 ICS950201AF
Q34 used only for EMI issue
R846 2N3904S
10K-0603 MULTSEL0=0 -> 4X Iref
VCC3
MULTSEL0=1 -> 6X Iref
(4) SKTOCC# Trace less 0.2"
B
PRIMARY IDE BLOCK ATA100 IDE CONNECTORS SECONDARY IDE BLOCK
B
IDE1
* Trace Width : 5mils IDE2
CN-BH-D2x20-1:21-BL-ZBT-S1 * Trace Spacing : 7mils D2x20-1:21-WH-SBT
HDRST# R847 33-0603 1 2 HDRST# R848 33-0603 1 2
(24) HDRST#
PDD7 3 4 PDD8 * Length(longest)-Length(shortest)<0.5" SDD7 3 4 SDD8
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 * Trace Length less than 6" SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
(12) PD_DREQ 21 22 (12) SD_DREQ 21 22
(12) PD_IOW# 23 24 (12) SD_IOW# 23 24
(12) PD_IOR# 25 26 (12) SD_IOR# 25 26
(12) PD_IORDY 27 28 (12) SD_IORDY 27 28
(12) PD_DACK# 29 30 (12) SD_DACK# 29 30
(11) IRQ14 31 32 (11) IRQ15 31 32
(12) PD_A1 33 34 PD_DET (11) (12) SD_A1 33 34 SD_DET (11)
(12) PD_A0 35 36 PD_A2 (12) (12) SD_A0 35 36 SD_A2 (12)
(12) PD_CS#1 37 38 PD_CS#3 (12) (12) SD_CS#1 37 38 SD_CS#3 (12)
(27) PD_LED 39 40 (27) SD_LED 39 40
R849 R850
R851 C487 R852 C488 R853 C489 R854 C490
4.7K-0603 10K-0603 10K-0603 4.7K-0603 10K-0603 10K-0603
A VCC5 VCC3 VCC5 VCC3 A
X_220p-0603 4700p-0603 X_220p-0603 4700p-0603
MICRO-STAR INT'L CO.,LTD.
PDD[0..15] (12)
Title
SDD[0..15] (12) MAIN CLOCK GEN / IDE
Size Document Number Rev
Custom MS-6557 2.1A
Date: Thursday, November 28, 2002 Sheet 3 of 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK For ITP debug CPU GTL REFERNCE VOLTAGE BLOCK
R1391 0-0603 DBRESET#
DBRESET# (12,19,27)
ITPCLK#
(6) HA#[3..31] ITPCLK# (3)
ITPCLK VCCP
ITPCLK (3)
VID[0..4] (23) Length < 1.5inch.
R227
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
2/3*Vccp 49.9RST
VID2
VID1
VID0
VID4
VID3
D GTLREF1 D
A3~A16#, HREQ#0~4 is strobed by HADSTB#0
AD26
AC26
AE25
A17~A35# is strobed by HADSTB#1 C260 C261 C237 R226
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
1u-0603 100RST
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
T5
T4
T2
T1
L2
L3
L6
U19A
220p-0603 0.1u-0603
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
DBR#
VCC_SENSE
VSS_SENSE
ITP_CLK1
ITP_CLK0
VID4#
VID3#
VID2#
VID1#
VID0#
HDBI#0 E21
(6) HDBI#[0..3] DBI0#
HDBI#1 G25 AA21 GTLREF1 Every pin put one 220pF cap near it.
HDBI#2 DBI1# GTLREF3
P26 DBI2# GTLREF2 AA6
HDBI#3 V21 F20 Trace Width 15mils, Space 15mils.
DBI3# GTLREF1
GTLREF0 F6
AC3 IERR# BPM#5
Keep the voltage dividers within 1.5 inches of the
V6 MCERR# BPM5# AB4
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