Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6551
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8 7 6 5 4 3 2 1
Cover Sheet 1 Version 10
Block Diagram 2 MS-6551 10/15/2001 Update
GPIO Spec. 3 INTEL (R) Brookdale Chipset
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Power Delivery Map 4
Clock CY28324 & ATA100 IDE CONNECTORS 5 CPU:
Willamette/Northwood mPGA-478B Processor
mPGA478-B INTEL CPU Sockets 6 -7
INTEL Brookdale MCH -- North Bridge 8-9 System Brookdale Chipset:
INTEL ICH2 -- South Bridge 10-11 INTEL MCH (North Bridge) +
INTEL ICH2 (South Bridge)
LPC I/O W83627HF 12
AC'97 Codec 13 On Board Chipset:
C
Audio Amp TL072 & GAME 14 BIOS -- FWH C
AC'97 Codec -- AD1881
FWH -- BIOS & CNR RISER 15
LPC Super I/O -- W83627HF
DDR MEMORY 16-17 Clock Generation -- ICS 950208
AGP 4X SLOT (1.5V) 18 LAN -- INTEL 82562EM/ET
PCI SLOT 1 & 2 & 3 19
PCI SLOT 4 & 5 20
Front Panel & Connectors 21
B
USB & FAN Connectors 22 Expansion Slots: B
SM READER &4 CHANNEL AUDIO 23 AGP2.0 SLOT * 1
PCI2.2 SLOT * 5
Votlage Regulator 24
CNR SLOT * 1
Intersil HIP6301 PWM 25 ISA SLOT * 1 (Share PCI5)
IO Connectors 26
LAN INTEL 82562EM/ET 27
PCI TO ISA BRIDGE AND ISA SLOT 28-29
A
JUMPER SETTING 30 A
MANUAL 31 Title Rev
M i c ro-Star MS-6551 10
Design Guide 32-34 Document Number
Cover Sheet
Last Revision Date:
Monday, October 15, 2001 Sheet 1 of 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AGP
4X(1.5V)
AGP CONN
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.2 Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
4 X (66MHz) AGP
AGP 4X
(1.5V) MCH: Memory
Controller HUB
( 5 93PINS/FCBGA) (133MHz)
DDR 1:3
VRM
AGP
CONN
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C C
ICH2: I/O PCI (33MHz)
PCI Slots 1:5
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
(48MHz)
PCI TO ISA BRIDGE ISA SLOT 1
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3 CNR Riser
(Shared slot)
AC '97 Audio
Hardware FWH: Firmware HUB AMP
Monitor Codec
SIO
Line Out
Telephone In
MIC In
B
Audio In B
LAN
Line In
PS2 Mouse & Parallel (1) Floppy Disk Stuffing
MEMORY WINBOND
Keyboard Serial (2) Drive CONN Options CD-ROM
STICK 518D
RJ45
A A
Title Rev
M i c ro-Star MS-6551 10
Document Number
Block Diagram
Last Revision Date:
Thursday, October 11, 2001 Sheet 2 of 34
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
ICH2
D GPIO Pin Type Function D
GPIO 0 I PCI TO ISA REQA#
GPIO 1 I Non Connect (PREQ#5)
GPIO 2 I INTE#
GPIO 3 I INTF#
GPIO 4 I INTG#
DEVICE ICH INT Pin IDSEL
GPIO 5 I INTH#
GPIO 6 I CNR Detect
FWH PCI Slot 1 INTA# AD16
GPIO Pin Type Function INTB#
GPIO 7 I None
INTC#
GPI 0 I ATA IDE 1 Detect
GPIO 8 I LAN Wake Up INTD#
C
GPI 1 I ATA IDE 2 Detect C
GPIO 9 I AC'97 Serial Data In
PCI Slot 2 INTB# AD17
GPI 2 I Reserved
GPIO 10 I Non Connect INTC#
GPI 3 I Reserved INTD#
GPIO 11 I Non Connect
INTA#
GPIO 12 I External SMI
GPIO 13 I LPC PME DLED PCI Slot 3 INTC# AD18
INTD#
GPIO 14~15 I Not Implemented GPIO Pin Type Function INTA#
INTB#
GPIO 16 O PCI TO ISA GNTA# GP32 I/OD DLED1
GPIO 17 O Non Connect (PGNT#5) GP24 I/OD DLED2 PCI Slot 4 INTD#
AD19
INTA#
GPIO 18 O Not Implemented GP34 I/OD DLED3
INTB#
B
GPIO 19 O Non Connect GP33 I/OD DLED4 INTC# B
GPIO 20 O Non Connect
PCI Slot 5 INTB#
AD21
GPIO 21 O PCI TO ISA NOGO INTC#
INTD#
GPIO 22 OD Audio 4 channel control
INTA#
GPIO 23 O BIOS Locked/Unlocked
GPIO 24 O Non Connect
GPIO 25 O Lan Status Input
GPIO 26 O Non Connect
GPIO 27 I/O Non Connect
GPIO 28 I/O LAN ENABLE/DISABLE
A A
GPIO 29~31 I/O Not Implemented
Title Rev
M i c ro-Star MS-6551 10
Document Number
GPIO Spec.
Last Revision Date:
Thursday, October 11, 2001 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1
Power Delivery Map
A T X 12V POWER Supply
D D
3.3V 5V 5VSB 12V
1A
VRM9.2 P r ocessor Core
Processor Vtt
Power
Translator
1.5V VREG MCH Core 1.5V
ACPI IC
MCH Vtt
MCH AGP
OP 1.8V VREG M C H H UB Interface 1.8V
M C H Memory sdr 3.3V
C C
3.3V
DUAL
FET P C - 1 3 3 System Memory 3.3V
3.3V VREG
I C H2 Core 1.8V
ICH2 I/O 3.3V
I C H 2 Resume 1.8V
1.8V VREG I C H 2 Resume I/O 1.8V
5V TO 3.3V ICH2 RTC 3.3V
RESISTOR
ICH2 5V
FWH 3.3V
B B
L P C Super I/O 3.3V
C L OCK GEN 3.3V
H A R D WARE AUDIO 3.3V
P C I LAN 3.3V/2.5V
5 V D u a l For USB and K/B
A A
Title Rev
M i c ro-Star MS-6551 10
Document Number
Power Delivery Map
Last Revision Date:
Thursday, October 11, 2001 Sheet 4 of 34
5 4 3 2 1
8 7 6 5 4 3 2 1
CP5 *Trace less 0.5"
2 1
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
CPUCLK R285 49.9RST
X_601S/0805 U18 CPUCLK# R286 49.9RST CN12 X_10p
FB17 39 41 R302 33RST CPUCLK MCHCLK R287 49.9RST CPUCLK 8 7
VCC3 CPU_VDD CPU0 CPUCLK (6)
40 R299 33RST CPUCLK# MCHCLK# R288 49.9RST CPUCLK# 6 5
+
CPU0# CPUCLK# (6)
CB163 Rubycon CT30 CB162 CB169 MCHCLK 4 3
104P 105P/0805 104P 36 38 R300 33RST MCHCLK MCHCLK# 2 1
CPU_GND CPU1 37 R301 33RST MCHCLK (8)
MCHCLK# MCHCLK# (8) C_STP C198 10P
D for good filtering from 10K~1M CPU1# P_STP C199 10P D
46
ELS10/16-B MREF_VDD 45 C_STP
CB170 3VMREF/CPU_STP# 44 P_STP
Trace less 0.2"
104P 3VMREF#/PCI_STP# CN13 X_10p
43 49.9ohm for 50ohm M/B impedance
CP7 MREF_GND MCH_66 8 7
2 1 32 31 1 2 MCH_66 MCH_66 (8) ICH_66 6 5
3V66_VDD 3V66_0 30 RN50 3 4 ICH_66 AGPCLK 4 3
3V66_1 ICH_66 (11)
CB172 28 8P4R-33 5 6 AGPCLK 2 1
104P 29
3V66_GND
3V66_2
3V66_3
27 C204 22P 7 8 AGPCLK (18) CLOCK STRAPPING RESISTORS
X_601S/0805 1 2 SIO_PCLK SIO_PCLK (12) CN14 X_10p
6 FS2 RN56 3 4 FWH_PCLK FWH_PCLK (15)
FS4 R359 10K VCC3V SIO_PCLK 8 7
FB18 VCC3V 9 FS2/PCI_F0 7 FS3 5 6 8P4R-33 FS3 R365 10K VCC3V FWH_PCLK 6 5
VCC3 PCI_VDD FS3/PCI_F1 8 MODE FS2 7 8 ICH_PCLK 4 3
+
MODE/PCI_F2 ICH_PCLK (10)
CB208 Rubycon CT35 CB198 CB199 7 8 FS1 R344 X_10K VCC3V ICH_PCLK 2 1
104P 105P/0805 104P 5 10 FS4 RN55 5 6 MS_CLK MS_CLK (23) R345 10K
PCI_GND FS4/PCI0 11 3 4 PCICLK3 PCICLK0 CN15 2 1 X_10p
for good filtering from 10K~1M PCI1 PCICLK3 (20)
18 12 8P4R-33 1 2 PCICLK4 PCICLK4 (20) FS0 R353 10K VCC3V PCICLK1 4 3
ELS10/16-B PCI_VDD PCI2 14 RN57 7 8 PCICLK0 R355 X_10K PCICLK2 6 5
CB200 PCI3 15 5 6 PCICLK1 PCICLK0 (19)
PCICLK1 (19) ISAPCLK 8 7
104P PCI4 PCICLK2 PCICLK4 C239 X_10P
13 16 3 4 PCICLK2 (19)
PCI_GND PCI5 17 8P4R-33 1 2 ISAPCLK R363 10K VCC3V PCICLK3 C238 X_10P
*Put GND copper under Clock Gen. PCI6 ISAPCLK (28)
FS2 R364 X_10K MS_CLK C237 X_10P
connect to every GND pin 24
48_VDD 22 FS0 R360 33 ICH_48 ICH_48 C241 X_10P
* 40 mils Trace on Layer 4 FS0/48MHz ICH_48 (11)
CB201 23 FS1 R354 33 SIO_48 MODE R358 10K SIO_48 C232 10P
with GND copper around it 104P 21 FS1/24_48MHz R367 33 SIO_48 (12)
MS_48 MS_48 (23) MS_48 C248 10P
48_GND
* put close to every power pin 2
C C
REF_VDD 48 R315 33 ICH_14 MUL0 R331 10K VCC3V
* Trace Width 7mils. VCC3 CB193 MUL0/REF0
1 MUL1 R339
MUL0 33 OSC
ICH_14 (11) R332 X_10K OSC C228 10P
MUL1/REF1 OSC (29)
104P 47 ICH_14 C206 10P
* Same Group spacing 15mils REF_GND MUL1 R347 X_10K VCC3V
34 3 C221 18P R349 10K VCC3
* Different Group spacing 30mils CORE_VDD X1 32pF
Trace less 0.2"
R362 CB171 X3 14M-32pf-HC49S-D
* Different mode spacing 7mils on itself 104P 33 4 C215 18P CRST# R306 10K VCC3V C178 X_104P
10K CORE_GND X2
(11,12,15,16) SMBCLK SMBCLK 26 35 R284 475RST C200 103P
SMBDATA 25 SCLK IREF SMBCLK R328 1K
(11,12,15,16) SMBDATA SDATA VCC3
20 CRST# R313 0 CLK_RST# CLK_RST# (21) 6/2/2001 SMBDATA R327 1K C197 X_104P
R361 0 19 RST# 42 R283 4.7K VCC3V
VTT_GD# PWR_DN# VCC3V C217 X_104P
VCCP R378 220 Q32 ICS 950208/CY28323/4 C_STP R297 X_1K VCC3V
2N3904S P_STP R298 X_1K
R30 R371 X_1K For Cypress
+12V 28324 used only for EMI issue
Q4
10K 2N3904S
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
R29
1K CB4 ATA100 IDE CONNECTORS
105P/0805 R239 4.7K IDE1 R270 4.7K IDE2
D2x20-1:21-BL-ZBT D2x20-1:21-WH-SBT
HD_RST# R237 33 1 2 HD_RST# R238 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
B (11) PDD[0..7] PDD6 PDD9 PDD[8..15] (11) (11) SDD[0..7] SDD6 SDD[8..15] (11) B
5 6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 C297 103P 19
21 22 VCC3 21 22
(11) PD_DREQ 23 24 (11) SD_DREQ 23 24
(11) PD_IOW# (11) SD_IOW#
(11) PD_IOR# 25 26 (11) SD_IOR# 25 26
27 28 R190 470 FOR EMI 27 28 R162 470
(11) PD_IORDY 29 30 (11) SD_IORDY 29 30
(11) PD_DACK# (11) SD_DACK#
(10) IRQ14 31 32 (10) IRQ15 31 32
(11) PD_A1 33 34 PD_DET (15) (11) SD_A1 33 34 SD_DET (15)
(11) PD_A0 35 36 PD_A2 (11) (11) SD_A0 35 36 SD_A2 (11)
(11) PD_CS#1 37 38 PD_CS#3 (11) (11) SD_CS#1 37 38 SD_CS#3 (11)
(21) PD_LED 39 40 (21) SD_LED 39 40
C113 R183 C106 C116 R185 C124 * Trace Width : 5mils
VCC5 R155 8.2K X_220P 10K X_472P VCC5 R148 8.2K X_220P 10K X_472P * Trace Spacing : 7mils
VCC3 VCC3 * Length(longest)-Length(shortest)<0.5"
* Trace Length less than 5"
VCC3 R391 330
R392 X_1K VCC5
A RESET BLOCK VCC5_SB A
R417 HD_RST#
X_4.7K
R389 330 VCC3 R409 330 VCC3 R402 X_4.7K Q34 Title Rev
X_2N3904S
(10) PCIRST#
PCIRST# 1 2
PCIRST#1 (8)
PCIRST# 3 4
PCIRST#2 (12,18,19,20)
M i c ro-Star MS-6551 10
PCIRST# R406 4.7K Q35
U23A U23B X_2N3904S Document Number
DM7407-SOIC14 C273 DM7407-SOIC14 PCIRST# 11 10 HD_RST#
Clock CY28323/4 & ATA100 IDE
(VCC5_STR) (VCC5_STR) R403
X_10P U23E Last Revision Date:
10K DM7407-SOIC14 Sheet of
Sunday, October 21, 2001 5 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK
VCCPS+ (25)
(8) HA#[3..31] VCCPS- (25)
VID[0..4] (12,25)
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
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