Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6552
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8 7 6 5 4 3 2 1
Version 0A
Cover Sheet
Block Diagram
1
2
MS-6552 (LEGEND) 1002
INTEL (R) Brookdale Chipset
Power Delivery Map 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
GPIO Spec. 4
Clock ICS94208 & ATA100 IDE CONNECTORS 5
mPGA478-B INTEL CPU Sockets 6-7
INTEL Brookdale MCH -- North Bridge 8-9
INTEL ICH2 -- South Bridge 10 - 11 CPU:
Willamette/Northwood mPGA-478B Processor
LPC I/O W83627HF 12
AC'97 Codec 13
C
System Brookdale Chipset: C
Audio Amp TL072 & GAME 14
INTEL MCH (North Bridge) +
FWH -- BIOS & CNR RISER 15 INTEL ICH2 (South Bridge)
DDR DIMM1,2 16 On Board Chipset:
DDR DAMPING 17 BIOS -- FWH
DDR TERMINATION & DDR 2.5V POWER 18 LPC Super I/O -- W83627HF
AGP 4X SLOT (1.5V) 19 Clock Generation -- ICS94208
PCI SLOT 1 & 2 & 3 20
B B
Front Panel & Connectors 21
USB & FAN Connectors 22 Expansion Slots:
AGP2.0 SLOT * 1
CPU_VID CONTROL 23
PCI2.2 SLOT * 3
Votlage Regulator 24 CNR SLOT * 1
HIP6301V CPU Power ( PWM )-VRM9.0 25
IO Connectors 26
Realtek RTL8100(L) LAN 27
A A
JUMPER SETTING 28
Title Rev
MANUAL 29 M i c ro-Star MS-6552 0A
Document Number
30 Cover Sheet
Last Revision Date:
Monday, October 01, 2001 Sheet 1 of 35
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D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.0 Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
AGP 4 X (66MHz) AGP
4X(1.5V) AGP 4X
(1.5V) MCH: Memory
AGP CONN
Controller HUB
( 5 93PINS/FCBGA) ( D D R200 or 266MHz)
DDR DIMM1:2
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Heceta Hardware SM Bus C
Monitor ICH2: I/O PCI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Audio /
(48MHz) C-MEDIA
CMI8738
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3 CNR Riser
(Shared slot)
AC '97 Audio
FWH: Firmware HUB AMP
Codec
PCI LAN / SIO
Realtek Line Out
Telephone In
RTL8100 MIC In
B
Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
CD-ROM
Keyboard Serial (2) Drive CONN
A A
Title Rev
M i c ro-Star MS-6552 OA
Document Number
Block Diagram
Last Revision Date:
Wednesday, September 05,2001 Sheet 2 of 35
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Power Delivery Map
A T X 1 2V POWER Supply
D D
3.3V 5V 5VSB 12V
1A
VRM9.2 Processor Core
Processor Vtt
Power
Translator
1.5V VREG MCH Core 1.5V
ACPI IC
MCH Vtt
MCH AGP
OP 1.8V VREG M C H H U B Interface 1.8V
M C H Memory sdr 3.3V
C C
3.3V
DUAL FET
D D R S ystem Memory 2.5V
3.3V VREG
2.5V FET
ICH2 Core 1.8V
ICH2 I/O 3.3V
I C H 2 Resume 1.8V
1.8V VREG I C H 2 Resume I/O 3.3V
5V TO 3.3V ICH2 RTC 3.3V
RESISTOR
ICH2 5V
FWH 3.3V
B B
L P C Super I/O 3.3V
C L OCK GEN 3.3V
H A R D WARE AUDIO 3.3V
P C I LAN 3.3V/2.5V
5 V D u a l For USB and K/B
A A
Title Rev
M i c ro-Star MS-6552 0A
Document Number
Power Delivery Map
Last Revision Date:
Wednesday, September 05,2001 Sheet 3 of 35
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH2
GPIO Pin Type Function
GPIO 0 I Non Connect
GPIO 1 I Non Connect
GPIO 2~4 I Not Implemented
DEVICE ICH INT Pin IDSEL
GPIO 5 I Non Connect
GPIO 6 I AC97 Enabled/Disabled
FWH PCI Slot 1 INTA# AD16
GPIO Pin Type Function INTB#
GPIO 7 I None
INTC#
C
GPI 0 I ATA IDE 1 Detect C
GPIO 8 I LAN Wake Up INTD#
GPI 1 I ATA IDE 2 Detect
GPIO 9 I AC'97 Serial Data In
PCI Slot 2 INTB# AD17
GPI 2 I Reserved
GPIO 10 I Non Connect INTC#
GPI 3 I Reserved INTD#
GPIO 11 I Non Connect
INTA#
GPIO 12 I External SMI
PCI Slot 3 INTC# AD18
GPIO 13 I LPC PME
INTD#
GPIO 14~15 I Not Implemented INTA#
INTB#
GPIO 16 O Non Connect
GPIO 17 O Non Connect PCI Audio INTD#/INTE# AD23
INTA#
B
GPIO 18 O Not Implemented B
INTB#
GPIO 19 O Not Implemented INTC#
GPIO 20 O Non
PCI Lan INTC#/INTF# AD22
GPIO 21 O Not Implemented INTD#
INTA#
GPIO 22 O Non
INTB#
GPIO 23 OD BIOS Locked/Unlocked
GPIO 24 O Non
GPIO 25 O Non
GPIO 26 O Non
GPIO 27 I/O Non
A A
GPIO 28 I/O Non
GPIO 29~31 I/O Not Implemented
Title Rev
M i c ro-Star MS-6552 0A
Document Number
GPIO Spec.
Last Revision Date:
Wednesday, September 05,2001 Sheet 4 of 35
5 4 3 2 1
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*Trace less 0.5"
X_COPPER CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
CP12
CPUCLK R233 49.9RST
U18 CPUCLK# R234 49.9RST
FB18 X_0/0805 39 41 R246 33 CPUCLK MCHCLK R229 49.9RST
VCC3 CPU_VDD CPU0 CPUCLK 6
40 R247 33 CPUCLK# CPUCLK# 6 MCHCLK# R230 49.9RST
CB145 Rubycon CB229 CB144 CB154 CPU0#
104P 102P 105P 104P 36 38 R239 47 MCHCLK
CPU_GND CPU1 37 R240 47 MCHCLK 8
MCHCLK# MCHCLK# 8
CN16
D
CPU1# D
for good filtering from 10K~1M VCC3C 46 8P4C-10P
MREF_VDD 45 C_STP MCH_66 1 2
CB151 3VMREF/CPU_STP# 44 P_STP
Trace less 0.2" ICH_66 3 4
CB238 104P 43 3VMREF#/PCI_STP# AGPCLK
49.9ohm for 50ohm M/B impedance 5 6
MREF_GND 7 8
VCC3 32 31 1 2 MCH_66 MCH_66 8
X_104P X_COPPER 3V66_VDD 3V66_0 30 RN17 3 4 ICH_66 CN18
3V66_1 ICH_66 11
CP13 CB153 28 8P4R-33 5 6 AGPCLK 8P4C-10P
R228 104P 29
3V66_GND
3V66_2
3V66_3
27 7 8 C157 10P AGPCLK 19 CLOCK STRAPPING RESISTORS SIO_PCLK 8 7
X_0 3V66_3 RN25 FWH_PCLK 6 5
6 FS2 7 8 ICH_PCLK 4 3
FB20 X_0/0805 VCC3V 9 FS2/PCI_F0 7 FS3 5 6 ICH_PCLK FS4 R324 10K VCC3V 2 1
VCC3 PCI_VDD FS3/PCI_F1 8 ICH_PCLK 10
MODE 3 4 FWH_PCLK FS3 R334 10K VCC3V
+
MODE/PCI_F2 FWH_PCLK 15
CB166 Rubycon CT36 CB178 CB183 1 2 SIO_PCLK CN17
104P 105P 104P 5 10 SIO_PCLK 12
FS4 FS1 R282 X_10K VCC3V 8P4C-10P
PCI_GND FS4/PCI0 11 R283 10K PCICLK0 7 8
X_ELS10U/16V-B PCI1 APIC_CLK 8P4R-33 PCICLK1
18 12 5 6
for good filtering from 10K~1M PCI_VDD PCI2 14 7 8 PCICLK0 PCICLK2 3 4
CB177 PCI3 15 RN24 5 6 PCICLK1 PCICLK0 20
PCICLK1 20 FS0 R321 10K VCC3V PCICLK3 1 2
104P 13 PCI4 8P4R-33 3 PCICLK2 R322 X_10K
16 4 PCICLK2 20
PCI_GND PCI5 17 1 2 PCICLK3
*Put GND copper under Clock Gen. PCI6 PCICLK3 27
FS2 R326 X_10K
connect to every GND pin 24 R325 10K VCC3V
48_VDD 22 FS0 R307 33 ICH_48 APIC_CLK C177 X_10P
* 40 mils Trace on Layer 4 FS0/48MHz ICH_48 11
CB164 23 FS1 R281 33 SIO_48 MODE R336 X_10K
with GND copper around it 104P 21 FS1/24_48MHz SIO_48 12
48_GND
* put close to every power pin 2
C C
REF_VDD 48 MUL0 R251 33 ICH_14 MUL0 R241 X_10K VCC3V ICH_48 C175 10P
* Trace Width 7mils. MUL0/REF0 ICH_14 11 MUL0=0 MUL0=1
CB165 1 MUL1 R231 10K SIO_48 C169 10P
104P 47 MUL1/REF1
* Same Group spacing 15mils REF_GND Ioh=6*Iref
Voh=0.71V MUL1 R316 10K VCC3V
VCC3C 34 3 C171 18P R315 X_10K
* Different Group spacing 30mils CORE_VDD X1 32pF
CB152 X1 14.318MHZ/32PF
* Different mode spacing 7mils on itself 104P 33 4 C166 18P CRST# R305 10K VCC3V ICH_14 C164 10P
CORE_GND X2
SMBCLK 26 35 R227 475RST
R323 VTT_GD# 11,12,15,16 SMBCLK SCLK IREF
VCC3 11,12,15,16 SMBDATA SMBDATA 25 SMBCLK R255 1K used only for EMI issue
10K SDATA 20 CRST# R306 X_0 FP_RST# SMBDATA R254 1K VCC3
RST# FP_RST# 21
R318 VTT_GD# 19
X_1K 42 R245 4.7K VCC3V
VCC3V Trace less 0.2"
Q36 VTT_GD# PWR_DN#
VCCP 2N3904S ICS950208 C_STP R242 X_1K VCC3V
R304 220 ICS950208 P_STP R235 X_1K
CY28323
+12V Q61
X_2N3904S
R735 X
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
R736 X C328
X
ATA100 IDE CONNECTORS
R190 X_4.7K IDE1 R186 X_4.7K IDE2
YJ220-CB-1 YJ220-CW-1
HD_RST# R188 33 1 2 HD_RST# R187 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
B 11 PDD[0..7] PDD6 PDD9 PDD[8..15] 11 11 SDD[0..7] SDD6 SDD9 SDD[8..15] 11 B
5 6 5 6
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
11 PD_DREQ 21 22 11 SD_DREQ 21 22
11 PD_IOW# 23 24 11 SD_IOW# 23 24
11 PD_IOR# 25 26 11 SD_IOR# 25 26
27 28 R129 470 27 28 R128 470
11 PD_IORDY 29 30 11 SD_IORDY 29 30
11 PD_DACK# 11 SD_DACK#
10 IRQ14 31 32 10 IRQ15 31 32
11 PD_A1 33 34 PD_DET 15 11 SD_A1 33 34 SD_DET 15
11 PD_A0 35 36 PD_A2 11 11 SD_A0 35 36 SD_A2 11
11 PD_CS#1 37 38 PD_CS#3 11 11 SD_CS#1 37 38 SD_CS#3 11
R189 33 39 40 R101 33 39 40
21 PD_LED 21 SD_LED
C79 R119 C76 C81 R120 C77
R191 8.2K 47P 10K X_473P VCC5 VCC3 R103 8.2K 47P 10K X_473P
VCC5 VCC5
VCC3 C238 102P VCC3
R407 X_1K VCC5
A RESET BLOCK PCIRST# 9 8 HD_RST# VCC3 A
R406 1K VCC5_SB
U21D R724 X_0
7407S R384 HD_RST#
R388 330 VCC3 (VCC5_STR) R197 330 VCC3 Title Rev
4.7K
10 PCIRST#
PCIRST# 1 2
PCIRST#1 8,12,15,27
PCIRST# 3 4
PCIRST#2 19,20
R386 M i c ro-Star MS-6552 0A
PCIRST# 4.7K R387 4.7K Q48
U21A U21B 2N3904S Document Number
7407S C199 7407S Q43
Clock CY28323/4 & ATA100 IDE
(VCC5_STR) (VCC5_STR) 2N3904S
X_10P R385 10K Last Revision Date:
Thursday, September 27, 2001 Sheet 5 of 35
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCPS+ 25 VCCP
8 HA#[3..31] VCCPS- 25
R81
2/3*Vccp 49.9RST
VID[0..4] 12,25
GTLREF1
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
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