Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6553
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1
Cover Sheet
Block Diagram
1
2
ZZTOP (MS-6553) Version 0B
10/16/2001 Update
AMD 462pins SocketA CPU - Signals 3 Nvidia (R) Crush11(nForce IGP 64) + MCP Chipset
AMD Althon/Duron/Palomino Socket 462 Processor
AMD 462pins SocketA CPU - Power 4
CRUSH11 - Host Signals 5 CPU:
AMD Althon/Duron/Palomino Socket 462 Processor
CRUSH11 - Memory Signals 6
CRUSH11 -AGP & LDT Signals 7 System Chipset:
CRUSH11- Power & Manual 8 Nvidia nForce IGP 64 (North Bridge)
MCP - PCI & LDT Signals 9 MCP Wep (South Bridge)
MCP - CPU & IDE & LPC & MAC & USB Signals 10
On Board Chipset:
LPC I/O - LPC47B367 11
BIOS -- LPC EEPROM
AC97 Audio - AD1885 12 AC'97 Codec -- AD1885
A
LAN & LPC Flash EEPROM 13 LPC Super I/O -- LPC47B367 A
LAN -- ICS1893AF
DDR System Memory 14
AGP 1.5V Slot & PCI Expansion Riser 15
Expansion Slots:
PCI Slots 16
AGP2.0 SLOT (1.5V) * 1
ATA33/66/100 IDE & Video Connectors 17 PCI2.2 SLOT * 3
H/W Monitor & FAN & USB Connectors 18
PLL Delay & VID Select 19 Intersil PWM:
ATX & Front Panel 20 Controller: HIP6301
Driver: HIP6601 + HIP6602
System & LDT & DDR Regulators 21
VRM 9.2 - Intersil 6301 22 Regulators
GPIO 23 System : SC1544
Revision History 1 - 2 24 - 25 DDR VTT: CM8500
LDT : IRU3037 MSI
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Title
COVER SHEET
Size Document Number Rev
ZZTOP (MS-6553) 0B
Date: Tuesday, October 16, 2001 Sheet 1 of 25
1
1
VRM 9.2
Intersil 6301
3-Phase PWM
462-Pin Socket Processor Block Diagram
K7 FSB
4X w/Fast Write
AGP 1.5V
Connector 64bit DDR
2 DDR
CRUSH 11 DIMM
Analog Modules
Video (1+1)
Out
LDT Link
IDE Primary UltraDMA 33/66/100
PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
IDE Secondary
MCP-1 PCI ADDR/DATA
USB Port 0
A A
USB Port 1
USB Port 2 USB
LPC Bus
USB Port 3
USB Port 4
LPC SIO
USB Port 5 SMSC
LPC47B367
AC'97 Link
AD1885
AC'97 Codec
MII
10/100BaseT
PHY
Flash Keyboard Floopy Parallel Serial
ICS1893AF
Mouse
MICRO-STAR INt'L CO., LTD.
MSI H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Title
BLOCK DIAGRAM
Size Document Number Rev
ZZTOP (MS-6553) 0B
Date: Tuesday, October 16, 2001 Sheet 2 of 25
1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK
CPU Clock Multiplier AMD HDT Debug Port
U13A
(5) SDATA#[0..63] SDATA#0 AA35 AE1 A20M# A20M# (10)
SDATA#1 W37 SDATA0 A20M AG1 FERR
SDATA#2 W35 SDATA1 FERR AJ3 CPUINIT# VCORE
SDATA2 INIT CPUINIT# (10)
2
4
6
8
SDATA#3 Y35 AL1 INTR FID2 1 2
SDATA#4 U35 SDATA3 INTR AJ1 IGNNE# INTR (10) FID1 3 4 RN5 VCORE R38 RN14 R33
SDATA4 IGNNE IGNNE# (10)
SDATA#5 U33 AN3 NMI FID0 5 6 4.7K 510 510 510
SDATA#6 SDATA5 NMI CPURST# NMI (10) FID3
S37 AG3 CPURST# (10) 7 8
SDATA6 RESET
1
3
5
7
SDATA#7 S33 AN5 SMI# JTAG1
SDATA#8 AA33 SDATA7 SMI AC1 STPCLK# SMI# (10) 1 2 CPU_TCK
D SDATA#9 AE37 SDATA8 STPCLK STPCLK# (10) SSHIFTEN 3 VCC TCK 4 CPU_TMS D
SDATA#10 AC33 SDATA9 AE3 CPU_OK SINTVAL 5 SHIFT TMS 6 SCANCLK1
SDATA#11 AC37 SDATA10 PWROK C594 X_10p CPU_OK (20) SCANCLK2 7 INTEVAL SC1 8 CPU_TDI
SDATA#12 Y37 SDATA11 CFID[3:0] => CPU Clock Multiplier SC2 TDI 10 CPU_TRST#
SDATA#13 AA37 SDATA12 N1 APICCLK_CPU 11 TRST# 12 CPU_TDO
SDATA#14 AC35 SDATA13 PICCLK N3 APICD0# APICCLK_CPU (5) DBREQ# 13 GND TDO 14 DBRDY
SDATA14 PICD0/BYPASSCLK APICD0# (10) DBREQ# DBRDY
SDATA#15 S35 N5 APICD1# CPURST# 15 16 PLLTEST#
SDATA#16 Q37 SDATA15 PICD1/BYPASSCLK APICD1# (10) CPURST# TEST#
SDATA#17 Q35 SDATA16 AG13 COREFB# X_AMD HDT
SDATA17 COREFB- COREFB# (22)
SDATA#18 N37 AG11 COREFB
SDATA#19 J33 SDATA18 COREFB+ COREFB (22)
1
3
5
7
SDATA#20 G33 SDATA19 AN17 CPUCLK_R
SDATA#21 G37 SDATA20 CLKIN AL17 CPUCLK#_R RN16
SDATA#22 E37 SDATA21 CLKIN 270
SDATA#23 G35 SDATA22 AN19
SDATA23 RSTCLK
2
4
6
8
SDATA#24 Q33 AL19
SDATA#25 N33 SDATA24 RSTCLK
SDATA#26 L33 SDATA25 AL21 CLKOUT
SDATA#27 N35 SDATA26 K7CLKOUT AN21 CLKOUT#
SDATA#28 L37 SDATA27 K7CLKOUT
SDATA#29 J37 SDATA28
SDATA#30 A37 SDATA29 AJ13
SDATA#31 E35 SDATA30
SDATA31
ANALOG CPU SYSCLK BLOCK CPU FERR BLOCK CPU K7CLKOUT BLOCK
SDATA#32 E31 AA5 VREFMODE
SDATA#33 E29 SDATA32 SYSVREFMODE W5 VREF_SYS
SDATA#34 A27 SDATA33 VREF_SYS VCORE VCORE VCORE
SDATA#35 A25 SDATA34 AC5 ZN
SDATA#36 E21 SDATA35 ZN
AE5 ZP (5) CPUCLK CLKOUT R100 100
462-Pin Socket
SDATA36 ZP VCORE
C SDATA#37 C23 R99 100 C
SDATA#38 C27 SDATA37 AJ25 PLLBP# CPUCLK_R C67 680p R87 X_60.4RST R15 R24
SDATA#39 A23 SDATA38 PLLBYPASS
AN15 PLBYCLK 680 150
SDATA#40 A35 SDATA39 PLLBYPASSCLK AL15 PLBYCLK#
SDATA#41 C35 SDATA40 PLLBYPASSCLK R89 CLKOUT# R96 100
SDATA#42 C33 SDATA41 AN13 FERR# (10) VCORE
PLLMON1 X_301RST R95 100
Part 1
SDATA#43 C31 SDATA42 PLLMON1 AL13 PLLMON2
SDATA#44 A29 SDATA43 PLLMON2 AC3 PLLTEST# CPUCLK#_R C82 680p R90 X_60.4RST FERR
SDATA#45 C29 SDATA44 PLLTEST
SDATA#46 E23 SDATA45 Q6
SDATA#47 C25 SDATA46 S1 SCANCLK1 YFET-FDV301N SOT-23
SDATA#48 E17 SDATA47 SCANCLK1 S5 SCANCLK2 (5) CPUCLK#
SDATA#49 E13 SDATA48 SCANCLK2 S3 SINTVAL * Trace lengths of CLKOUT and
SDATA#50 E11 SDATA49 SCANINTEVAL Q5 SSHIFTEN CLOSE SOCKET462 M e a s u r e F E R R # & IGNNE Delay Time CLKOUT# are between 2" and 3"
SDATA#51 C15 SDATA50 SCANSHIFTEN
SDATA#52 E9 SDATA51 AA1 DBRDY
SDATA#53 A13 SDATA52 DBRDY
AA3 DBREQ#
SDATA#54 C9 SDATA53 DBREQ AL3 FLUSH#
SDATA#55 A9 SDATA54 FLUSH
SDATA#56 C21 SDATA55 Q1 CPU_TCK CPU SYSCLK REFERNCE BLOCK CPU ZN / ZP BLOCK CPU APIC BLOCK
SDATA#57 A21 SDATA56 TCK U1 CPU_TDI
SDATA#58 E19 SDATA57 TDI U5 CPU_TDO
SDATA#59 C19 SDATA58 TDO Q3 CPU_TMS VCORE
SDATA#60 C17 SDATA59 TMS U3 CPU_TRST#
SDATA#61 A11 SDATA60 TRST ZN R69 40.2RST APICD0# R27 453RST
SDATA#62 A17 SDATA61 R78 VCORE VCC2_5
SDATA#63 A15 SDATA62 L1 VIDA0 0.5 * VCORE 110RST ZP R68 56.2RST APICD1# R29 453RST
SDATA63 VID0 L3 VIDA1 VIDA[0..4] (19) VREF_SYS
VID1 L5 VIDA2 APICCLK_CPU R165 X_453RST
B
DICLK#0 W33 VID2 L7 VIDA3 C50 C44 C45 R77 B
(5) DICLK#[0..3] DICLK#1 J35 SDATAINCLK0 VID3 J7 VIDA4 10u-0805 0.1u 0.047u 110RST
SDATAINCLK1 VID4
CLOSE SOCKET462
DICLK#2 E27
DICLK#3 E15 SDATAINCLK2
SDATAINCLK3 W1 FID0 match the transmission line
AN33 FID0 W3 FID1 FID[0..3] (5)
(5) DIVAL# SDATAINVAL FID1
CLOSE SOCKET462 Push-pull compensation circuit
Y1 FID2
DOCLK#0 AE35 FID2 Y3 FID3
(5) DOCLK#[0..3] DOCLK#1 C37 SDATAOUTCLK0 FID3
DOCLK#2 A33 SDATAOUTCLK1
DOCLK#3 C11 SDATAOUTCLK2 U37
SDATAOUTCLK3 SCHECK0 Y33
DOVAL# AL31
SDTATOUTVAL
SCHECK1
SCHECK2
L35 CPU PULL-UP / DOWN BLOCK
E33
AIN#0 AJ29 SCHECK3 E25
AIN#1 AL29 SADDIN0 SCHECK4 A31
AIN#2 AG33 SADDIN1 SCHECK5 C13 NMI 1 2 AIN#0 R116 680 PLBYCLK R84 100
(5) AIN#[2..14] AIN#3 SADDIN2 SCHECK6 INTR VCORE VCORE VCORE
AJ37 A19 3 4 RN3 AIN#1 R117 680 R83 100
AIN#4 AL35 SADDIN3 SCHECK7 SMI# 5 6 680
AIN#5 AE33 SADDIN4 J1 CPUINIT# 7 8 PLLMON1 R79 56 PLBYCLK# R81 100
SADDIN5 SADDOUT0 VCORE
AIN#6 AJ35 J3 PLLMON2 R74 56 R80 100
AIN#7 AG37 SADDIN6 SADDOUT1 C7 AOUT#2
AIN#8 AL33 SADDIN7 SADDOUT2 A7 AOUT#3 AOUT#[2..14] (5) STPCLK# 1 2 FLUSH# R40 680
AIN#9 AN37 SADDIN8 SADDOUT3 E5 AOUT#4 A20M# 3 4 RN6 PLLBP# R113 680
AIN#10 AL37 SADDIN9 SADDOUT4 A5 AOUT#5 IGNNE# 5 6 680 VREFMODE R62 X_1K
AIN#11 AG35 SADDIN10 SADDOUT5 E7 AOUT#6 CPURST# 7 8 R61 270 VCORE
AIN#12 AN29 SADDIN11 SADDOUT6 C1 AOUT#7
AIN#13 AN35 SADDIN12 SADDOUT7 C5 AOUT#8 FILVAL# R132 270
A AIN#14 AN31 SADDIN13 SADDOUT8 C3 AOUT#9 DOVAL# R126 270 A
SADDIN14 SADDOUT9 VREFMODE=Low=No voltage scaling
G1 AOUT#10
AJ33 SADDOUT10 E1 AOUT#11
(5) AICLK# SADDINCLK SADDOUT11 A3 AOUT#12
AJ21 SADDOUT12 G5 AOUT#13 MICRO-STAR INt'L CO., LTD.
(5) CFWDRST AL23 CLKFWDRST SADDOUT13 G3 AOUT#14 MSI H/W Project Leader : Andy Chen
(5) CONNECT AN23 CONNECT SADDOUT14 H/W Project Engineer : Prudence Wang
(5) PROCRDY FILVAL# AJ31 PROCRDY E3 C543 X_4.7u-0805 COREFB R72 10K Title
SFILLVAL SADDOUTCLK AOCLK# (5) VCORE VCORE
N12-4620011-F02 C544 X_4.7u-0805 AMD Socket462 CPU (Signal)
C545 X_4.7u-0805 COREFB# R76 0 Size Document Number Rev
**All CPU interface are 2.5V tolerant** ZZTOP (MS-6553) 0B
Put in Solder
Date: Tuesday, October 16, 2001 Sheet 3 of 25
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VOLTAGE BLOCK
VCORE VCCA_PLL
0 ~ 100 mA (50mA)
2.25 ~ 2.75 V
AM34
AM30
AM26
AM22
AM18
AM14
AM10
AH26
AH22
AH18
AH14
AH10
AB30
AK36
AK34
AK30
AK26
AK22
AK18
AK14
AK10
AB36
AB34
AB32
AF14
AF18
AF22
AF26
AF36
AF34
AJ23
AM2
AH4
AH2
AD6
AD4
AD2
AC7
H12
H16
H20
H24
D32
D28
D24
D20
D16
D12
P30
X30
AL5
X36
X34
X32
P36
P34
P32
K36
K34
K32
B36
B32
B28
B24
B20
B16
B12
T30
T36
T34
T32
F36
F34
F32
F28
F24
F20
F16
F12
AJ5
M8
M4
M6
M2
Z8
Z6
Z4
Z2
R8
R6
R4
R2
H4
H2
D8
D4
D2
V8
V6
V4
V2
B8
B4
U13C
VCC_Z
VCC_CORE100
VCC_CORE101
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VCC_CORE96
VCC_CORE97
VCC_CORE98
VCC_CORE99
VCC_A
U13B AO1 YY24
N12-4620011-F02 AO2 GND GND YY23
D AO3 GND GND YY22 D
AO4 GND GND YY21
AA31 GND GND YY20
NC1 AC31 GND YY19
AD30 NC2 AE31 GND YY18
AD8 VCC_SRAM1 NC3 AG23 YY1 GND YY17
AF10 VCC_SRAM2 NC6 AG25 YY2 GND GND YY16
AF28 VCC_SRAM3 NC7 AG31 YY3 GND GND YY15
AF30 VCC_SRAM4 NC8 AG5 YY4 GND GND YY14
AF32 VCC_SRAM5 NC9 AJ11 YY5 GND GND YY13
AF6 VCC_SRAM6 NC10 AJ15 YY6 GND GND YY12
AF8 VCC_SRAM7 NC11 AJ17 YY7 GND GND YY11
AH30 VCC_SRAM8 NC12 AJ19 YY8 GND GND
AH8 VCC_SRAM9 NC13 AJ27 YY9 GND XX1
AJ9 VCC_SRAM11 NC15 AL11 YY10 GND GND
XX2
AK8 VCC_SRAM13 NC16 AN11 GND GND
AL9 VCC_SRAM14 NC17 AN9
AM8 VCC_SRAM16 NC18 G11 N12-4620011-F02
F30 VCC_SRAM17 NC19 G13
F8 VCC_SRAM19 NC20 G27
VCC_SRAM20 NC21
H10
VCC_SRAM21 NC22
G29 For 1.5GHz CPU Fan Holes
H28 G31
462-Pin Socket
H30 VCC_SRAM22 NC23 J31
H32 VCC_SRAM23 NC24 J5
H6 VCC_SRAM24 NC25 L31
H8 VCC_SRAM25 NC27 N31
Part 2
K30 VCC_SRAM26 NC28 Q31
K8 VCC_SRAM27 NC29 S31
VCC_SRAM28 NC30 THERMDP# (18)
C AJ7 S7 C
AL7 VCC_SRAM29 NC31 U31 C20
AN7 VCC_SRAM30 NC32 U7 1000p
VCC_SRAM31 NC33 THERMDN# (18)
W31
NC34 W7
NC35 Y31
NC36 Y5
NC37 AG19
G25 NC42 G21
G17 KEY4 NC43 AG21
G9 KEY6 NC44 G19
N7 KEY8 NC45
Y7 KEY10 AN27
AG7 KEY12 BP0_CUT AL27
AG15 KEY14 BP1_CUT AN25
AG29 KEY16 BP2_CUT AL25
KEY18 BP3_CUT
VCCA_PLL trace length from the regulator to
the PGA must less be 0.75"
B2 VSS100
AM4 VSS101
AK6 VSS102
AM6 VSS103
VSS104
VSS_Z
Z30 VSS10
AB8 VSS11
AF12VSS12
AF16VSS13
AF20VSS14
AF24VSS15
VSS16
AK32VSS17
AK28VSS18
AK24VSS19
AK20VSS20
AK16VSS21
AK12VSS22
AK4 VSS23
AK2 VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
AF4 VSS35
AF2 VSS37
VSS38
VSS39
VSS40
AB6 VSS41
AB4 VSS42
AB2 VSS43
VSS44
Z34 VSS45
Z32 VSS46
X6 VSS47
VSS48
X4 VSS49
X2 VSS50
V36 VSS51
V34 VSS52
V32 VSS53
T6 VSS54
T4 VSS55
T2 VSS56
R36 VSS57
R34 VSS58
VSS59
R32 VSS60
P6 VSS61
P4 VSS62
P2 VSS63
M36 VSS64
M34 VSS65
M32 VSS66
K6 VSS67
K4 VSS68
K2 VSS69
VSS70
H36 VSS71
H34 VSS72
F26 VSS73
F22 VSS74
F18 VSS75
F14 VSS76
F10 VSS77
F6 VSS78
F4 VSS79
F2 VSS80
VSS81
D36 VSS82
D34 VSS83
D30 VSS84
D26 VSS85
D22 VSS86
D18 VSS87
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