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Cover Sheet
Block Diagram
1
2
MS-6571 Version
20A
Clock ICS950218AF & ATA100 IDE CONNECTORS 3 INTEL (R) Brookdale-GE Chipset
Willamette/Northwood 478pin mPGA-B Processor Schematics
mPGA478-B INTEL CPU Sockets 4-5
INTEL Brookdale-G GMCH -- North Bridge 6-8 CPU:
Willamette/Northwood mPGA-478B Processor
INTEL ICH4 -- South Bridge 9-10
LPC I/O -- W83627HF 11 INTEL (R) Brookdale-GE Chipset
AC'97 Codec / Audio Jack / Front Audio Connector 12 INTEL GMCH (North Bridge) +
INTEL ICH4 (South Bridge)
Audio Amplifier & CD Panel Play & W518D_SB 13
DDR DIMM1&2 and DDR Terminator Resistor 14-15 On Board Chipset:
AGP Slot 16 BIOS -- FWH
AC'97 Codec -- ALC201A/650
PCI SLOT 1 & 2 & 3 & 4 & 5 17,27
LPC Super I/O -- W83627HF
Floppy, KB/MS, Com/Printer Ports 18 LAN -- INTEL 82562EZ
USB Connectors 19 82540EM
Front Panel , ATX Connectors 20
Expansion Slots:
FWH & CNR Riser 21
AGP2.0 SLOT * 1
VRM 9.0 Regulator (CPU Power) 22 PCI2.2 SLOT * 5
SMBUS Isolation & FAN & AGP 1.5V 23 ISA SLOT * 1
CNR SLOT * 1
LAN -- INTEL 82562EM/ET 24
Bluetooth header supported
W83302D(MS5) ACPI Controller 25
VGA Connector 26
PCI_ISA Bridge 28-29
Manual Part 30
Micro Star Restricted Secret
Last Schematic Update Date: Title
Document Number
COVER SHEET
MS-6571
Rev
20A
Friday, July 12, 2002 MICRO-STAR INT'L CO.,LTD. L a s t Revision Date:
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 33
(100/133MHz)
VCC12 Power VRM 9.2 Willamette/Northwood Clock
Supply CONN Socket (mPGA478-B) (100/133MHz) Generator
Scalable Bus
AGP 4X (1.5V) 4X (66MHz) AGP
VGA CONN
GMCH: Graphic &
Memory
Controller HUB (200/266 MHz)
DDR DIMM1,2
HUB Interface
(14.318MHz)
IDE CONN 1&2 ATA33/ATA66/ATA100
ICH4: I/O PCI (33MHz)
PCI Slots 1:5
USB Port 0:1 (48MHz) Controller HUB
USB Front Panel PCI (33MHz)
LAN Controller
(33MHz)
(33MHz)
USB Port 2:3
USB Front Panel PCI_ISA
LPC Bus Bridge
AC Link AC '97 Audio
Winbond Codec
W518D_SB ISA SLOT
USB Port 4:5
USB Rear Panel MIC In
Winbond FWH: Firmware HUB CNR
Line In
LPC I/O
W83627HF Brookdale -G Chipset Line Out
CD-ROM (Option)
PS2 Mouse & Parallel (1) Floppy Disk
Hardware Keyboard Serial (2) Drive
Monitor
Model option table
Model type Function BOM Config ERP BOM No.
MS6571 For Legend
Micro Star Restricted Secret
Title Rev
BLOCK DIAGRAM
Document Number 20A
MS-6571
MICRO-STAR INT'L CO.,LTD. L a s t R e v i s i on Date:
T h u r s d a y , J u ly 11, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 2 of 33
CLOCK GENERATOR BLOCK
*Trace < 0.5"
Shut Source Termination Resistors Pull-Down Capacitors
U1 CPUCLK R1 49.9
FB1 80_0805 VCC3V 39 41 CPU0 R2 27.4 CPUCLK CPUCLK# R3 49.9 CPUCLK C1 X
VCC3 CPU_VDD CPUCLK0 CPU0# R4 27.4 CPUCLK# CPUCLK 4 MCHCLK R5 49.9 CPUCLK# C2 X
40
CB1 CB273 CB274 CB2 CPUCLK0# CPUCLK# 4
MCHCLK# R7 49.9 MCHCLK C3 X
0.1u X 0.1u 0.1u 36 38 CPU1 R10 27.4 MCHCLK MCHCLK# C4 X
CPU_GND CPUCLK1 CPU1# MCHCLK 6
37 R12 27.4 MCHCLK#
MCHCLK# 6
CPUCLK1# CN10 X
filtering from 10K~1M 46 2 1
MREF_VDD AGPCLK
* Put GND copper under Clock Gen. 45 Trace less 0.2" 4 3
CB3 CPUCLK2 44 ICH_66 6 5
connect to every GND pin 0.1u 43 CPUCLK2# RN84 33
49.9ohm for 50ohm M/B impedance MCH_66 8 7
MREF_GND 1 2
* 40 mils Trace on Layer 4 32 31 RMCH_66 3 4 MCH_66
3V66_VDD 3V66_0 MCH_66 6
with GND copper around 30 RICH_66 5 6 ICH_66 PCICLK0 C13 X
* put close to every power pin CB4 3V66_1 28 RAGPCLK 7 8 AGPCLK ICH_66 10 CLOCK STRAPPING RESISTORS PCICLK1 C14 X
it 0.1u 29 3V66_2 27 SEL66_48# R589 33 AGPCLK 16 PCICLK2 C15 X
3V66_GND 3V66_48/SEL66_48# SIO_48 11
* Trace Width 7mils. 6 FS2 R15 33 PCICLK0 R18 1.5K VCC3V CN11 X
FS2/PCI_F0 FS3 R929 33 PCICLK4 PCICLK0 17 PCICLK3
* Same Group spacing 15mils 9 7 PCICLK4 27 2 1
PCI_VDD FS3/PCI_F1 8 SEL48_24# R931 33 PCICLK5 SIO_PCLK 4 3
CB5 SEL48_24#/PCI_F2 PCICLK5 28 FWH_PCLK 6 5
* Different Group spacing 30mils 0.1u 5 10 FS4 R952 X_33PCICLK6 FS1 R22 1.5K ICH_PCLK 8 7
PCI_GND FS4/PCI0 RPCICLK1 R16 33 PCICLK1 PCICLK6 13 BSEL0 4,6
* Differentical mode spacing 7mils on itself 11 PCICLK1 17
18 PCI1 12 RPCICLK2 R17 33 PCICLK2
PCI_VDD PCI2 14 RLAN_PCLK 7 8 PCICLK3 PCICLK2 17 SIO_48 C376 10p_0603
CB6 PCI3 RSIO_PCLK PCICLK3 27
15 5 6 SIO_PCLK SIO_PCLK 11 FS4 FS3 FS2 FS1 FS0 CPU (MHz) ICH_48 C20 10p_0603
0.1u 13 PCI4 16 RFWH_PCLK 3 4 FWH_PCLK DOT_CLK C21 0
PCI_GND PCI5 17 RICH_PCLK 1 2 ICH_PCLK FWH_PCLK 21 ICH_14 C16 X
PCI6 ICH_PCLK 9 1 1 1 0 1 100 MHz
VCC3 FB2 80_0805
VDDA3V 24 RN2 33 1 1 1 1 1 133 MHz PCICLK6 C846 X
CB7 CB275 C24 48_VDD 22 FS0 R26 33 ICH_48 MS_48 C847 X
0.1u FS0/48MHz ICH_48 10
X 0.01u 23 FS1 R27 X_33 DOT_CLK
DOT_CLK 6
21 FS1/24_48MHz R953 X_33 MS_48 SMBCLK_ISO R29 4.7K PCICLK4 C822 X
48_GND MS_48 13 SMBDATA_ISO R32 4.7K VCC3 PCICLK5 C823 X
for good filtering from 10K~1M 2 OSC C824 X
C26 REF_VDD 48 MULTSEL0 R25 33 ICH_14 LAN_CLK R700 33
MUL0/REF0 ICH_14 10 30 LAN_CLK
0.01u 1 MULTSEL1 R930 33 OSC
OSC 29 RN75
47 MUL1/REF1 8.2K
REF_GND FS4 1 2 VCC3V
34 3 X1 C23 10p_0603 SEL48_24# 3 4
C27 CORE_VDD X1 FS3 5 6
0.01u X1 14M-32pf-HC49S-D FS2 7 8
used only for EMI issue
33 4 X2 32pF C25 10p_0603 Trace less 0.2"
CORE_GND X2 FS0 R740 10K
11,14,21,23,25,31 SMBCLK_ISO 26 35 R28 475 Iref = 2.32mA
SCLK IREF
11,14,21,23,25,31 SMBDATA_ISO 25
SDATA 20 R860 22 SEL66_48# R741 10K
R30 1K 19 RESET# 42 FP_RST# 10,20,25 MULTSEL0 R742 10K
VCC3
C
VTT_GD# PWR_DN#
VCCP R35 B Q1 ICS-ICS950218AF-SSOP48
220 PWR_DN# R590 33 VCC3V
MULTSEL1 R998 10K VCC3V
NPN-MBT3904LT1-S-SOT23
E
MULTSEL0=0 -> 6X Iref
MULTSEL0=1 -> 7X Iref
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
ATA100 IDE CONNECTORS
IDE1 IDE2
D2x20-1:21-BL-ZBT D2x20-1:21-WH-SBT
HD_RST#1 R43 33HD_RST#1R 1 2 HD_RST#2 R44 33 HD_RST#2R 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
10 PDD[0..7] PDD6 PDD9 PDD[8..15] 10 10 SDD[0..7] SDD6 SDD9 SDD[8..15] 10
5 6 5 6
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 * Trace Width : 5mils SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 * Trace Spacing : 7mils 19
10 PD_DREQ 21 22 10 SD_DREQ 21 22
23 24 * Length(longest)-Length(shortest)<0.5" 23 24
10 PD_IOW# 10 SD_IOW#
10 PD_IOR# 25 26 10 SD_IOR# 25 26
10 PD_IORDY 27 28 * Trace Length less than 6" 10 SD_IORDY 27 28
10 PD_DACK# 29 30 10 SD_DACK# 29 30
31 32 31 32
9 IRQ14 33 34 9 IRQ15 33 34
10 PD_A1 35 36 PD_DET 21 10 SD_A1 35 36 SD_DET 21
10 PD_A0 37 38 PD_A2 10 10 SD_A0 37 38 SD_A2 10
10 PD_CS#1 PD_CS#3 10 10 SD_CS#1 SD_CS#3 10
39 40 39 40
20 PD_LED 20 SD_LED
R743 R744
R47 C29 R48 R49 C31 R50
4.7K 15K 15K
220p 10K 4.7K 220p 10K
VCC5 VCC3 VCC5 VCC3
R157 10K RST_GATE R158 1 2 120K
Micro Star Restricted Secret
+12V Title Rev
Clock & IDE Conn.
G
G
Q9 NDS7002A-S-SOT23 Q10 NDS7002A-S-SOT23 Document Number 20A
HD_RST# S D HD_RST#1 S D HD_RST#2 R949 0 HD_RST#1
MS-6571
25 HD_RST#
MICRO-STAR INT'L CO.,LTD. L a s t Revision Date:
T h u r sday, July 18, 2002
R950 X_0 No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 33
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
6 HA#[3..31]
VID[0..4] 11,22
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
HA#7
HA#6
HA#5
HA#4
HA#3
HA#8
VCCP
VID2
VID0
VID4
VID3
VID1
R54
AD26
AC26
AE25
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
2/3*Vccp 49.9
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
L2
L3
L6
CPU1A GTLREF1
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
DBR#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
VCC_SENSE
VID4#
VID3#
VID2#
VID1#
VID0#
VSS_SENSE
ITP_CLK1
ITP_CLK0
C34 C35 R55
HINV#[0..3] HINV#0 E21 220p 1u-0805 100
HINV#1 G25 DBI0# AA21 GTLREF1
HINV#2 P26 DBI1# GTLREF3 AA6
HINV#3 V21 DBI2# GTLREF2 F20
DBI3# GTLREF1 F6
GTLREF0
AC3
V6 IERR# AB4 BPM#5
B6 MCERR# BPM5# AA5 BPM#4
9 FERR# Y4 FERR# BPM4# Y6 BPM#3
9 STPCLK# AA3 STPCLK# BPM3# AC4 BPM#2
HINIT# W5 BINIT# BPM2# AB5
9 HINIT# AB2 INIT# BPM1# AC6
RSP# BPM0#
H5 H3 HREQ#4
Every pin put one 220pF cap near it.
6 HDBSY# H2 DBSY# REQ4# J3 HREQ#[0..4] 6
HREQ#3 Trace Width 7mils, Space 10mils.
6 HDRDY# J6 DRDY# REQ3# J4 HREQ#2
6 HTRDY# TRDY# REQ2# K5 HREQ#1 Keep the voltage divider within
G1 REQ1# J1 HREQ#0
6 HADS# G4 ADS# REQ0# 1.5" of the GETREF pin.
6 HLOCK# G2 LOCK# AD25
6 HBNR# F3 BNR# TESTHI12 A6 R59 49.9
6 HIT# HIT# TESTHI11 VCCP
E3 Y3 R60 49.9
6 HITM# D2 HITM# TESTHI10 W4 R61 49.9
6
6
HBPRI#
HDEFER# E2 BPRI# TESTHI9 U6 R62 49.9 CPU ITP BLOCK
DEFER# TESTHI8 AB22
ITP_TDI C1 ITPCLKOUT1 AA20
ITP_TDO D5 TDI ITPCLKOUT0 AC23
ITP_TMS F7 TDO TESTHI5 AC24
ITP_TRST# E6 TMS TESTHI4 AC20 ITP_TDI R79 150
TRST# TESTHI3 VCCP
ITP_TCK D4 AC21
B3 TCK TESTHI2 AA2 R592 49.9 ITP_TRST# R83 680
11 CPU_TMPA C4 THERMDA TESTHI1 AD24 VCCP
11 VTIN_GND TRMTRIP# A2 THERMDC ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo