Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6715
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1
Cover Sheet 1
Block Diagram
Revision History 1 - 3
2
3-5 VISE (MS-6715) Version 0C
10/21/2002 Updated
Intel mPGA478B CPU - Signals 6 Intel (R) Springdale (GMCH) + ICH5 Chipset
Intel Northwood & Prescott mPGA478B Processor
Intel mPGA478B CPU - Power 7
Intel Springdale - Host Signals 8
CPU:
Intel Springdale - Memory Signals 9
Intel Northwood/Prescott - 3.0G & Above
Intel Springdale - AGP & LDT Signals 10 System Chipset:
Intel ICH5 - PCI & IDE & AC97 Signals 11 Intel Springdale - GMCH (North Bridge)
Intel ICH5 - Other Signals 12
Intel ICH5 (South Bridge)
Clock - ICS ICS952606 & FWH & Manual 13 On Board Chipset:
LPC I/O - LPC47B387 14 BIOS -- FWH EEPROM
AC97 Audio - AD1981B 15
AC'97 Codec -- AD1981B
LPC Super I/O -- LPC47B387
A
Broadcom BCM5702 16 LAN -- CSR Interface A
DDR System Memory 1 & 2 17 CLOCK -- ICS952606 / CY28405
DDR System Memory 3 & 4 18
H/W Monitoring -- ADM1027
AGP 4X/8X Slot & PCI Riser Card 19 Main Memory:
PCI Slots 1 & 2 & 3 20 DDR2700 * 4 (Max 4GB)
ATA33/66/100 IDE & Video Connectors 21 Expansion Slots:
USB & LAN Connectors 22 PCI2.3 SLOT * 3
H/W Monitor & FAN 23 AGP4X/8X SLOT * 1
ATX & Front Panel 24 Intersil PWM:
AGP & MEMORY & USB Regulator Controller 25 Controller: HIP6556B
VCC_DAC & VTT Regulator & VR Thermal 26 Driver: HIP6602B * 2
VRM 10 - Intersil HIP 6556B + HIP 6602B 27 Regulators
MICRO-STAR INt'L CO., LTD.
PULL UP/ DOWN RESISTORS 28 System : FAN5236 MSI H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Title
COVER SHEET
GPIO 29 Size Document Number Rev
VISE (MS-6715) 0C
Date: Monday, October 21, 2002 Sheet 1 of 30
1
1
VRM 10
Intersil 6556
4-Phase PWM
Intel mPAG478B Processor Block Diagram
FSB
133/[email protected]/4.5GB/s
4X/8X w/Fast Write
AGP 1.5V
Connector [email protected]/s 64bit DDR 4 DDR
Springdale DIMM
Modules
Analog 133/[email protected]/2.7GB/s
Video
Out
Link
HCT
66MHz@266MB/s
UltraDMA
IDE Primary 33/66/100/133
PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
IDE Secondary 44.44MHz(W)/50MHz(R)@88.9/100MB/s
ICH5 PCI ADDR/DATA
USB Port 0
A 33MHz@133MB/s A
USB Port 1
USB Port 2
[email protected]/s
LPC Bus
USB Port 3 USB
USB Port 4 240MHz@60MB/s
LPC SIO
USB Port 5 SMSC
LPC47B387
USB Port 6
USB Port 7
AC'97 Link
AD1981B
AC'97 Codec [email protected]/s Flash Keyboard Floopy Parallel Serial
PCI Mouse
GIGA LAN
BCM5702 33MHz@133MB/s
MICRO-STAR INt'L CO., LTD.
MSI H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Title
BLOCK DIAGRAM
Size Document Number Rev
VISE (MS-6715) 0C
Date: Monday, October 21, 2002 Sheet 2 of 30
1
5 4 3 2 1
Revision Initial ver: 0AE0 on 07/31/2002 Revision change list from ver: 0AE3 to ver: 0AE4 on 8/14/2002 Revision change list from ver: 0AE4 to ver: 0AE5 on 08/16/2002
Schematic Initial on July 31. Sheet 13: Modify clock generator library. Sheet 17: Modify some block for customer request, detail list on below:
Sheet 14: Modify some block for customer request, detail list on below: (1) Add two 75 ohm divide resistors in DDR_VREF.
Revision change list from ver: 0AE0 to ver: 0AE1 on 08/01/2002
(1) Change SERIAL PORT 2 connector to 10 pin center-keyed shrouded header. (2) Change 110ohm to 56ohm on Rterm array resistors.
Sheet 1: Modify some txts.
(2) Add TI GD75232. (3) Add two divide 75ohm resistors pin 1.
Sheet 2: Modify some txts.
(3) Change label PS_ON to PS_ON#. Sheet 18: Modify some block for customer request, detail list on below:
Sheet 16: Move Lan connector to page 26.
Sheet 15: Modify some block for customer request, detail list on below: (1) Add two 75 ohm divide resistors in DDR_VREF.
D Sheet 25: Modify some block for customer request, detail list on below: D
(1) Delete Q7,Q8,Q10,Q11,Q12,Q34. (2) Change 110ohm to 56ohm on Rterm array resistors.
(1) Modify 5v USB power supplier.
(2) Modify this page same as reference schematic. (3) Add two divide 75ohm resistors pin 1.
(2) Modify 5V main power circuit.
Sheet 17: Exchange pin 103 and pin 167 on DIMM1 and DIMM2. Sheet 20: Modify some block for customer request, detail list on below:
(3) Modify GMCH VTT voltage supplier.
Sheet 18: Exchange pin 103 and pin 167 on DIMM3 and DIMM4. (1) Add 2pins header for support Prochot latch.
(4) Add GMCH VTT reference voltage circuit.
Sheet 21: Modify some block for customer request, detail list on below: Sheet 21: Modify some block for customer request, detail list on below:
Sheet 26: Modify some block for customer request, detail list on below:
(1) Add 33 ohm series resistors on Data 15:0 on Primary IDE. (1) Change R299 and R295 from 4.7Kohm to 8.2Kohm.
(1) Modify 3V standby power supplier.
(2) Add 33 ohm series resistors on Data 15:0 on Secondary IDE. Sheet 22: Modify some block for customer request, detail list on below:
(2) Change VTT_DDR to LP2995.
(3) Delete U12, NC7WZ08. (1) Add one usb power circuit to seperate port 0,1 and 2,3.
(3) Add lan magnetic circuit.
Sheet 24: Modify some block for customer request, detail list on below: (2) Change R315 and R313 from 21Kohm to 470Kohm.
(4) Modify Lan connector.
(1) Delete Q31, R376, R377,and R378. (3) Change R320 and R319 from 51Kohm to 560Kohm.
(5) Add 1.5V standby voltage.
(2) Change label PS_ON to PS_ON#. (4) Change C134 from 470pF to 1000pF.
Revision change list from ver: 0AE1 to ver: 0AE2 on 08/09/2002 (3) Delete U12, NC7WZ08. Sheet 24: Modify some block for customer request, detail list on below:
Sheet 8: Change VTT_FSB to capacitors termination on pin A15 and A21. Sheet 25: Change Q25 from 2N3904 to 2N7002. (1) Change R380 from 330ohm to 68ohm.
Sheet 9: Change VCC_DDR to capacitors termination on pin Sheet 27: Modify some block for customer request, detail list on below:
C
E35,E35,AA35,AR21 and AR15. Revision change list from ver: 0AE4 to ver: 0AE5 on 08/16/2002 C
(1) Change CT41-CT44 from 2200uF to 560uF.
Sheet 27: Change some bulk caps from 2200uF to 560uF. Sheet 6: Modify some block for customer request, detail list on below:
Sheet 28: Modify some block for customer request, detail list on below:
(1) All TESTHI pull up resistors change from 51ohm to 62ohm.
Revision change list from ver: 0AE2 to ver: 0AE3 on 08/13/2002 (1) Change label OC#3 to OC#7.
(2) Delete OPTIMZ label.
Sheet 12: Modify some block for customer request, detail list on below: (2) Add some divide resistors to CI_VREF and CI_SWING signals.
Sheet 7: Modify some block for customer request, detail list on below:
(1) Delete GP14 and GP15 on pin U21 and pin T20 on ICH5. (3) Change R1 from 100ohm to 200ohm and add a 200ohm resistor pull to VTT voltage.
(1) Delete EC1 and EC2.
(2) Add CHASIS_ID2 on pin V3 on ICH5. (4) Delete R14. and ITP_VCC direct connect to Vccp.
(2) Change L1 and L2 from 4.7uH to 10uH.
(3) Delete USB6+, USB6-, USB7+, and USB7-. (5) Change BPM# from 51ohm to 62ohm.
Sheet 8: Modify some block for customer request, detail list on below:
(4) Change FRONT_USB_DET# from pin C13 to pin D13 on ICH5. (6) Change R30 from 220ohm to 200ohm.
(1) Separate from VCCA_FSB and add 0.1uF cap to GND on pin A31.
Sheet 13: Modify some block for customer request, detail list on below: (7) Add two 0ohm resistors to support ITP or USB_ITP port.
(2) Change C225 from 0.22uF to 0.47uF.
(1) Modify clock generator library. (6) Change R17 from 27ohm to 47ohm.
Sheet 10: Modify some block for customer request, detail list on below:
(2) Change PCI clock label.
(1) Add 2pins header to pin T20. Revision change list from ver: 0AE5 to ver: 0AE6 on 08/19/2002
(3) Add strapping resistors.
(2) Change pin D14 and C14 to OC#2 signal. Sheet 25: Modify some block for customer request, detail list on below:
Sheet 17: Delete some caps on VCC_DDR.
(3) Change label OC#2 to OC#3. (1) Add 300 ohm resistor from BOOT to VCC_VID and change R423 to 10Kohms.
Sheet 18: Delete some caps on VCC_DDR.
B (4) Change label OC#3 to OC#7. (2) Change R411 and R415 to 3V_SW_CTRL# signal. B
Sheet 19: Delete some AGP termination resistors.
(5) Add label CI_VREF and CI_SWING to pin AF4 and AF2. Sheet 27: Modify some block for customer request, detail list on below:
Sheet 20: Change PCI clock label.
(6) Delete R65 on pin AG10. (1) Add Northwood FB network and Prescott FB network to VRM controlled by BOOT.
Sheet 22: Modify some block for customer request, detail list on below:
Sheet 11: Modify some block for customer request, detail list on below: (2) Change 110ohm to 56ohm on Rterm array resistors.
(1) Delete 2 ports USB, and one USB power.
(1) Add 0.1uF cap to pin F19. (3) Change R460,R464,R467,and R470 from 2.83Kohm to 3.3Kohm.
(2) Removed LAN connector to here.
(2) Add 0.1uF cap to pin Y5, AA4 and AB4. Sheet 28: Add teo 10Kohm pull down resistors to RSMRST# and ICH_GD signals.
Sheet 24: Modify some block for customer request, detail list on below:
(3) Add 0.1uF cap to pin F7 and F8.
(1) Change from GP14 to NC on pin 10 of F_P1. Revision change list from ver: 0AE6 to ver: 0AE7 on 08/20/2002
Sheet 12: Modify some block for customer request, detail list on below:
(2) Change from NC to CHASIS_ID2 on pin 15 of F_P1. Sheet 13: Modify some block for customer request, detail list on below:
(1) Change R102 from 0ohm to 10Kohm.
(3) Change from GP15 to CHASIS_ID0 on pin 17 of F_P1. (1) Change R495 from ICHPCLK to LANPCLK signal.
Sheet 13: Modify some block for customer request, detail list on below:
(4) Change from GND to CHASIS_ID1 on pin 18 of F_P1. (2) Change R496 from FWHPCLK to PCICLK0 signal.
(1) Change R154 and R152 from 300ohm to 330ohm.
(5) Pull VCC3_SB to pin C13 on ICH5. (3) Change R497 from LANPCLK to PCICLK1 signal.
(1) Change R151 from 2Kohm to 2.2Kohm.
Sheet 27: Modify some block for customer request, detail list on below: Sheet 16: Delete CB89,CB90,CB88,CB114, CB117, and CB118.
Sheet 15: Modify some block for customer request, detail list on below:
(1) Change R473 from 1Kohm to NC. Sheet 17: Change all component from 0603 to 0402.
(1) Add 47ohm resistor to AC_SDIN0.
(2) Change R475 from 0 ohm to NC. Sheet 18: Change all component from 0603 to 0402.
A
(2) Change R199 from 10ohm to 47ohm and add 47pF cap. A
(3) Change some bulk caps from 2200uF to 560uF.
(3) Change R219 and R209 from 4.7Kohm to 100ohm.
Sheet 28: Delete R89,R90,R91, and R92.
(4) Change R202, R203, R207, R208 from 6.8Kohm to 4.7Kohm. MICRO-STAR INt'L CO., LTD.
(5) Add divide 1Kohm pull down resistor to OUT_R and OUT_L signals. MSI H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
(6) Delete C71. Title
REVISION HISTORY - 1
Size Document Number Rev
VISE (MS-6715) 0C
Date: Monday, October 21, 2002 Sheet 3 of 30
5 4 3 2 1
5 4 3 2 1
Revision change list from ver: 0AE7 to ver: 0AE8 on 08/21/2002 Revision change list from ver: 0AE9 to ver: 0AEA on 08/26/2002 Revision change list from ver: 0AEC to ver: 0AED on 09/12/2002
Sheet 7: Change some caps of north side to not install. Sheet 23: Modify some block for customer request, detail list on below: Sheet 14: Modify some block for customer request, detail list on below:
Sheet 12: Modify some block for customer request, detail list on below: (1) Change H/W monitoring circuit. (1) Swap net BRD_V1 and FAN_CLAMP.
(1) Add LPC_DRQ#1 label on pin R2 on ICH5. (2) Change Fan circuit. (2) Delete R551, and change net 5V_IN to COMM_B_DET#.
(2) Change pin Y12 from INTRUDER# to HOOD_SENSE#. Sheet 24: Change Label from VCC3_SB to 3VSB. Sheet 15: Modify some block for customer request, detail list on below:
Sheet 13: Modify some block for customer request, detail list on below: Sheet 25: Change Label from VCC3_SB to 3VSB. (1) Change R196 to 3.3Kohm.
D
(1) Remove R143 and R142. Connect FWH RST# signal directly to PCIRST#. Sheet 26: Change Label from VCC3_SB to 3VSB. (2) Add a 270pF cap to GND and AGND, not install. D
(2) Delete R154,Q5,Q3, and R151. Sheet 27: Change Label from VCC3_SB to 3VSB. (3) Add a 1uF caps to MONO_L and MONO_L_R.
(3) Change R152 from 330 ohm to 8.2K ohm. Sheet 28: Change Label from VCC3_SB to 3VSB. (4) Add a 1uF caps to MONO_R and MONO_R_R.
(4) Add one resistor to SEC_PCLK signal and share with SIO_PCLK. (5) Change R501 and R555 to 130ohm.
Revision change list from ver: 0AEA to ver: 0AEB on 09/03/2002
(5) Delete INIT# BLOCK. (6) Change C218 from 4700pF to 0.01uF.
Sheet 6: Change CPU Symbol - pin F6=GTLREF3, pin F20=GTLREF2, pin
Sheet 14: Modify some block for customer request, detail list on below: AA6=GTLREF1, pin AA21=GTLREF0. Sheet 17: Change net DDR_VREF to DDR_VREF1.
(1) Change pin 44 to BRD_V1. Sheet 9: Modify some block for customer request, detail list on below: Sheet 18: Change net DDR_VREF to DDR_VREF2, and add two resistors.
(2) Change pin 45 to MB_ADPT_DET#. (1) Disconnect U28 pin E34 (GMCH) directly to VREF. Sheet 23: Modify some block for customer request, detail list on below:
(3) Change pin 47 to SEC_TPM_PRES. (2) Add a 2.2uF cap to this pin E34. (1) Modify H/W monitoring and FAN controller.
(4) Change pin 49 to MB_ADPT_DET#. Sheet 13: Modify some block for customer request, detail list on below: (2) Change U13 pin 22 from VCC_DDR to No Connect.
(5) Change pin 54 to FDD_2M. (1) Change R135 & R139 from 1K to 10K. Sheet 24: Add PROCHOT# LED.
(6) Add pin 104 to 5V_IN. (2) Add pullup resistor from BSEL0 to VCC3. Sheet 25: Modify some block for customer request, detail list on below:
Sheet 18: Change all component from 0603 to 0402. (3) Add pullup resistor from BSEL1 to VCC3. (1) Delete R394 and R401.
Sheet 20: Modify some block for customer request, detail list on below: Sheet 21: Change FB16, FB18 & FB20 to be the same as FB17, FB19 & FB21. (2) Change C166 to 0.01uF.
(1) Change TAP resistors from 4.7Kohm to 2.2Kohm. Sheet 25: Modify some block for customer request, detail list on below: (3) Change Q38 pin 5 and pin 6 to VCC5_STR.
C C
(2) Add a 2.2Kohm pull down resistor to PCIRST#1. (1) Change Q40 & Q41 to Depletion Mode JFETs. (4) Change Q39 pin 5 and pin 6 to VCC3.
Sheet 24: Add Security header. (2) Connect R400 to -12V. (5) Change Q38 pin 3 to PHASE_2V5.
Sheet 25: Change VCC5 & VCC3 Discharge Residual Voltage same as reference schematic. (3) Change R399 to a 39 ohm RNET and connect in parallel to VCC5. (6) Change Q39 pin 3 to PHASE_1V5.
(4) Change R405 to a 39 ohm RNET and connect in parallel to VCC3. (7) Change DZ5 to VCC5.
Revision change list from ver: 0AE8 to ver: 0AE9 on 08/23/2002
(5) Move R417 from Drain of Q51 to Source. (8) Change U15 pin 15 and 16 to VCC5_STR.
Sheet 16: Support BCM4401.
(6) Change R417 from 150 to 866 ohms. Sheet 26: Modify some block for customer request, detail list on below:
Sheet 20: Modify some block for customer request, detail list on below:
(7) Change R425 from 150 to 634ohms. (1) Add VR THERMAL BLOCK.
(1) Delete CT17.
(8) Change R426 from 150 to 499 ohms. (2) Add ICH5 VCCSUS1_5A, B, and C voltage regulatot to support this version fail
(2) Change CT16 from intall to not install. chipset.
Sheet 28: Change R46 & R50 to 150 ohms 1%.
Sheet 23: Delete CB284 and R324. Sheet 28: Modify some block for customer request, detail list on below:
Sheet 27: Change R456,R466,R479, and R489 from 1 ohm/1206 to 4.7ohm/0805. Revision change list from ver: 0AEB to ver: 0AEC on 09/09/2002 (1) Delete R35, IERR#.
Sheet 7: Delete 0.1uF caps on CPU side. (2) Change net GPI12 to PS_DETECT.
Revision change list from ver: 0AE9 to ver: 0AEA on 08/26/2002
Sheet 8: Change R41 from 24.9ohm to 20ohm. (3) Change net GPI7 to PROC_HOT#.
Sheet 11: Change Label from VCC3_SB to 3VSB.
Sheet 9: Modify some block for customer request, detail list on below: (4) Add Thermtrip Translation Block.
Sheet 13: Modify some block for customer request, detail list on below:
B (1) Disconnect U2 pin AR31 (GMCH). (5) Change RN3 pin 2 to No Connect. B
(1) Change Label from PCIRST# to PCIRST_ICH5#.
(2) Disconnect U2 pin AL35 (GMCH) and add single cap to it. (6) Delete C36, C37, and R100.
(2) Change all pull high resistors of clock generator from VCC3V to VCC3.
Sheet 17: Delete decoupling caps between VCC_DDR and VTT_DDR. (7) Delete net RTC_XI.
Sheet 14: Modify some block for customer request, detail list on below:
Sheet 18: Delete decoupling caps between VCC_DDR and VTT_DDR.
(1) Change Label from VCC3_SB to 3VSB. Revision change list from ver: 0AED to ver: 0AEE on 09/18/2002
Sheet 21: Change all arrary resistors from 0603 to 0402 on all IDE.
(2) Change pin 45 to GP25 and add a 4.7Kohm resistor to VCC3 on GP25. Sheet 11: Change U3 pin A5 from PREQ#A to BRD_ID1. Delete R72.
Sheet 22: Add secondary transformer to support 10M and 100M NIC.
(3) Add a label SYSMAG_INT on pin 61. Sheet 12: Modify some block for customer request, detail list on below:
(4) Change pin 44 to MB_ADPT_DET#. Revision change list from ver: 0AEC to ver: 0AED on 09/12/2002 (1) Change U3 pin G23 from BRD_ID1 to SATALED#.
(5) Change pin 49 to SEC_TPM_PRES. Sheet 6: Modify some block for customer request, detail list on below: (2) Change U3 pin U22 from RISER#2 to No Connect.
Sheet 15: Modify some block for customer request, detail list on below: (1) Disconnect CPU1 pin AC3, IERR# signal. (3) Change U3 pin T1 from BRD_ID0 to NIC_ENABLE#.
(1) Delete R514, R515, C81, C86, C88, C89. (2) Add a pull down resistor to CPU1 pin AE26, OPTIMIZ signal, and not install. (4) Change U3 pin V2 from SIO_PME# to PCI_PME#.
(2) Change R211 & R216 to 0 ohm. Sheet 7: Change R36 from 1Kohm to 2.43Kohm. (5) Change U3 pin F21 from CH_FAN_OVRD to BRD_ID0.
(3) Change C82 & C84 to 4.7uF. Sheet 11: Add RN91 to support VCCSUS1_5A,B,C voltage for ICH5. Sheet 13: Change R625 and R626 to 1Kohm.
(4) Change R209 & R219 to 4.7K. Sheet 12: Modify some block for customer request, detail list on below: Sheet 14: Modify some block for customer request, detail list on below:
(5) Add 0.22uF and 4.12K in series to pin1 of Front Audio Header. (1) Change net GPI12 to PS_DETECT. (1) Change U6 pin 29 from COMM_B_DET# to DDRC and add pull up to VCC3.
A A
(6) Add label bias circuit to pin 3 of Front Audio Header. (2) Add net FAN_CMD to pin U20. (2) Change R191 from 3VSB to VCC3.
(7) Add X_330 ohm from OUT_L to junction of C218 & R504. (3) Change net GPI7 to PROC_HOT#.
Sheet 16: Change Label from VCC3_SB to 3VSB. (4) Change R102 to 390Kohm, not install ,and a resistor to GND.
MICRO-STAR INt'L CO., LTD.
MSI H/W Project Leader : Andy Chen
Sheet 21: Change Label from VCC3_SB to 3VSB. (5) Delete net RTC_XI. H/W Project Engineer : Prudence Wang
Title
Sheet 22: Change Label from VCC3_SB to 3VSB. Sheet 14: Modify some block for customer request, detail list on below: REVISION HISTORY - 2
(1) Change net TRMTRIP# to SIO_TRMTRIP#. Size Document Number Rev
VISE (MS-6715) 0C
(2) Delete R551, and change net 5V_IN to COMM_B_DET#.
Date: Monday, October 21, 2002 Sheet 4 of 30
5 4 3 2 1
5 4 3 2 1
Revision change list from ver: 0AED to ver: 0AEE on 09/18/2002 Revision change list from ver: 0AE11 to ver: 0AE12 on 10/01/2002
Sheet 14: Modify some block for customer request, detail list on below: Sheet 13: Modify some block for customer request, detail list on below:
(3) Change U6 pin 8 from PLED to SUSLED. (1) Change SMBCLK to SMB_CLK.
(4) Change U6 pin 13 from SUSLED to PLED. (2) Change SMBDATA to SMB_DATA.
(5) Change U6 pin 14 from SIO_PME# to RI#. Sheet 17: Modify some block for customer request, detail list on below:
(6) Change U5 & U22 from 75232 to TI75185. (1) Change SMBCLK to SMB_CLK.
D Sheet 19: Change U11 pin 55 from RISER#2 to No Connect. Delete R148. (2) Change SMBDATA to SMB_DATA. D
Sheet 21: Modify some block for customer request, detail list on below: Sheet 18: Modify some block for customer request, detail list on below:
(1) Add 1K pull up from IDEA_RST# to VCC5. (1) Change SMBCLK to SMB_CLK.
(2) Add 1K pull up from IDEB_RST# to VCC5. (2) Change SMBDATA to SMB_DATA.
Sheet 22: Delete U32. Sheet 19: Add some caps between VCC3 and VCC5.
Sheet 23: Change CT53 and CT54 to 25V part. Sheet 20: Add some caps on VCC3 and VCC5.
Sheet 25: Change Q51 and Q53 to FDV301N. Sheet 23: Modify some block for customer request, detail list on below:
Sheet 26: Add U35 for support sata led on front panel. (1) Change SMBCLK to SMB_CLK.
Sheet 28: Modify some block for customer request, detail list on below: (2) Change SMBDATA to SMB_DATA.
(1) Add R36 62 ohms from TRMTRIP# to VCCP.
Revision change list from ver: 0AE12 to ver: 0BE0 on 10/16/2002
(2) Change R80 from TRMTRIP# to ICH_TRMTRIP#.
Sheet 8: Change U28 to install and R526 to not install.
Revision change list from ver: 0AEE to ver: 0AEF on 09/22/2002 Sheet 10: Add pin D10 to GND.
Sheet 14: Modify some block for customer request, detail list on below: Sheet 11: Change RN91 to not install.
(1) Change KBGND to GND on COM2. Sheet 12: Modify some block for customer request, detail list on below:
C C
(2) Delete FB3. (1) Add RSMRST# pull high resistor.
(3) Change U6 pin 14 from SIO_PME# to RI#. (2) Add PWRBTN# pull high resistor.
(4) Change U5 & U22 from 75232 to TI75185. (3) Change R628 to R102 to install.
Sheet 19: Change U11 pin 55 from RISER#2 to No Connect. Delete R148. Sheet 13: Add ICH66 pull down resistor.
Sheet 14: Modify some block for customer request, detail list on below:
Revision change list from ver: 0AEF to ver: 0AE10 on 09/27/2002
(1) Change RSLCT to SLCT.
Sheet 7: Modify some block for customer request, detail list on below:
(2) Change RPE to PE.
(1) Change EC32,46,5,30,15,23,49,45,25,and EC37 to not install.
Sheet 16: Modify some block for customer request, detail list on below:
(2) Change EC 8,42,21,43,38,28,29,36,17,16,39, and EC35 to not install.
(1) Add two resistors to VDD_PCI voltage.
Sheet 16: Modify some block for customer request, detail list on below:
(2) Delete DZ3.
(1) Change U9 pin H2 from PIRQ#H to PIRQ#E.
Sheet 17: Add some caps on VCC_DDR voltage.
(2) Change U9 pin C3 from PGNT#5 to PGNT#0.
Sheet 18: Add some caps on VTT_DDR voltage.
(3) Change U9 pin J3 from PREQ#5 to PREQ#0.
Sheet 22: Change LAN connector to popular 8pins.
Sheet 19: Modify some block for customer request, detail list on below:
Sheet 25: Modify some block for customer request, detail list on below:
B (1) Change AGP1 pin A6 from PIRQ#A to PIRQ#C. B
(1) Change FAN5236 circuit.
(2) Change AGP1 pin B6 from PIRQ#B to PIRQ#D.
(2) Change VCC5_STR circuit.
(3) Change U11 pin 5 from PIRQ#A to PIRQ#F.
(3) Change Q50 to TO-252.
(4) Change U11 pin 66 from PIRQ#B to PIRQ#G.
(4) Change VTT circuit some components to not install.
(5) Change U11 pin 6 from PIRQ#C to PIRQ#A.
Sheet 26: Move 1_5VSB voltage.
(6) Change U11 pin 67 from PIRQ#D to PIRQ#C.
Sheet 28: Change Q95 to 2N3906.
Sheet 20: Modify some block for customer request, detail list on below:
(1) Change PCI1 pin A17 from PGNT#0 to PGNT#5. Revision change list from ver: 0BE0 to ver: 0BE1 on 10/18/2002
(2) Change PCI1 pin B18 from PREQ#0 to PREQ#5. Sheet 13: Change pull high strapping to pull down.
Sheet 22: Change NIC_IDESEL to NIC_IDSEL. Sheet 15: Change some component to fix audio solution.
Sheet 27: Change CT35 to not install. Sheet 27: Change some components to fix VRM solution.
Sheet 30: Add two mini jumpers to support front panel.
Revision change list from ver: 0AE10 to ver: 0AE11 on 09/30/2002
Sheet 16: Modify some block for customer request, detail list on below:
(1) U9 pin P9 should connect to U31 pin 4.
A A
(2) U9 pin N9 should connect to U31 pin 3.
(3) U31 pin 1 should connect to U9 pin P10 (EE_DATA).
(4) U31 pin 2 should connect to U9 pin M10 (EE_CLK).
MICRO-STAR INt'L CO., LTD.
MSI H/W Project Leader : Andy Chen
Sheet 28: Add SMBBUS isolation block. H/W Project Engineer : Prudence Wang
Title
REVISION HISTORY - 3
Size Document Number Rev
VISE (MS-6715) 0C
Date: Monday, October 21, 2002 Sheet 5 of 30
5 4 3 2 1
8 7 6 5 4 3 2 1
ITP_DBR# (28)
CPU SIGNAL BLOCK
VCC_SENSE (27)
VSS_SENSE (27)
(8) HA#[3..31] VID_GD (7)
VID[0..5] (23,27)
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
D D
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID2
VID1
VID0
VID5
VID4
VID3
AD26
AC26
AE25
AD2
AD3
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
T5
T4
T2
T1
L2
L3
L6
CPU1A
A35#
A34#
A33#
A32#
A31#
A30#
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