Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6787
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8 7 6 5 4 3 2 1
MS-6787 Ver : 10D Cover Sheet
Block Diagram
1
2
VIA P4M266A + VT8235 Chipset CLOCK GEN 3
D D
CPU: Intel CPU Sockets 478 4-5
P4 Socket 478 VIA VT8751A P4M266A North Bridge 6-8
DDR1,2 SLOT 9
System Chipset: DDR TERMINATOR 10
VIA P4M266A + VT8235 AGP SLOT 11
On Board Chipset: VIA VT8235CD South Bridge 12 - 14
LPC Super I/O -- W83697HF LPC I/O(W83697HF) 15
C
Lan : Via PHY VT6103 KB / MS / LPT / COM Port / FAN Connector 16
C
AMR & ROM & Screw hole
17
Expansion Slots: PCI 1,2,3 SLOTS 18
AGP 3.0 Slot * 1 IDE & VGA Connector 19
DDR Slot * 2
PCI 2.2 Slot * 3 USB Connector 20
CNR Slot * 1 AC97 Audio CODEC & Connector 21
LAN VT6103 & Connector 22
B B
MS5 ACPI Controller & , Regulators 23
VRM9.0 INTERSIL HIP6302 24
Front Panel & ATX power Com & thermal protection 25
HISTORY 26
MODEL Config. ORCAD Config. Function Option ERP Number
MS6787 STD cfg6787-LAN STD STD 601-6787-020
A A
MSI
Micro-Star
Title
Cover Sheet
Size Document Number Rev
10B1
MS-6787
Date: Tuesday, February 17, 2004 Sheet 1 of 27
8 7 6 5 4 3 2 1
1
Block Diagram X'TEL
AGPCLK 66MHZ
14.318MHZ
VRM
ICS950910 Clock Generator
VLCLK66 66MHZ
CPUCLK, CPUCLK# 100/133MHZ
INT & PWR-MNG
P4 478-Pin Processor SBPCLK 33MHZ
NBHCLK, NBHCLK# 100/133MHZ
SIOPCLK 33MHZ
NBCLK66 66MHZ
ADDR
CTRL
DATA
PCICLK1,2,3 33MHZ
GUICLK 14.318MHZ LAN_PCLK 33MHZ
AGTL+ BUS
SIO_48M 48MHZ
ADDR
CTRL
DATA
DCLK_OUT 133MHZ
USBCLK 48MHZ
DCLK_FB 133MHZ
AGPCLK 66MHZ
VCORE SB14MHZ 14.318MHZ
AGP / ADD AGP BUS APICCLK 14.318MHZ
Slot
VT8751 (P4M266A) MDCLK0 ~ MDCLK5 133MHZ
MDCLK#0~MDCLK#5
BGA 664 Pin
DDR1
DDR2
VGA BUS
VGA DDR BUS
Connector
VDDQ 1.5V VCC2_5 VDIMM 2.5V
V- LINK BUS
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCICLK1,2,3 33MHZ
VLCLK66 66MHZ
A
IDE Primary UltraDMA 66/100
A
SBPCLK 33MHZ
USBCLK 48MHZ
IDE Secondary
VT8235 CD
SB14MHZ 14.318MHZ
INT & PWR-MNG
APICCLK 14.318MHZ
PCI BUS
AC'97 Link / LAN / EEPROM
AMR Slot VCC3SBY 3.3V VCC3 3.3V VT6103
MII Bus LAN Port
VCC25SBY 2.5V VCC2_5 2.5V
LAN Chip
ISA BUS
Onboard Flash ROM
BIOS
SIOPCLK 33MHZ
AC'97 Codec
USB 6 PORT LPC SIO SIO_48M 48MHZ
W83697HF
Audio port USB Port 5 USB Port 3 USB Port 1 Mouse Floopy Parallel Game Port
MSI MICRO-STAR INT'L CO.,LTD.
Title
USB Port 6 USB Port 4 USB Port 2 Keyboard Serial1,2 Block Diagram
Size Document Number Rev
10B1
MS-6787
Date: Tuesday, February 03, 2004 Sheet 2 of 27
1
5 4 3 2 1
CP9 X_COPPER
filtering from 10K~1M U16 Pull-Down Capacitors
FB10 X_80_0805 VCC3V 51
VCC3 CPU_VDD3.3
53 R210 27.4RST CPUCLK
CPUCLK 4
7774
CB20 CB17 CB5 CPUCLK R204 27.4RST CPUCLK# 7774 CPUCLK C225 X_10p
CPUCLK# 52 CPUCLK# 4
X_104P X_104P 104P 54 CPUCLK# C226 X_10p
CPU_GND3.3
FB7 VCC2.5A 50 NBHCLK C210 X_10p
VCC2_5 CPU_VDD2.5
X_80_0805 48 R206 27.4RST NBHCLK
NBHCLK 6
8533 NBHCLK# C219 X_10p
CB13 CPUCLKCS R205 27.4RST NBHCLK# 8534
CPUCLKCS# 49 NBHCLK# 6
CP6 104P 47 CPU_GND2.5
D D
X_COPPER 5 6 MODE R266 33 NBCLK66
NBCLK66 8
4939.17 NBCLK66 C254 X_10p
CB8 CB11 3V66_VDD Mode/AGP0 AGPCLK C255 X_10p
X_104P X_104P CB23 7 SEL_CK408 R267 33 AGPCLK
AGPCLK 11
3570.36 VLCLK66 C252 X_10p
104P SEL_CK408/K7/AGP1
9 8 R253 33 VLCLK66
VLCLK66 12
7477.03
3V66_GND PCISTOP#/AGP2
10 FS1 R280 33 SBPCLK
SBPCLK 12
1888.27 SBPCLK C258 X_10p
FS1/PCI_F
16 PCI_VDD
11 SEL_SDR/DDR R257 10K
SEL_SDR/DDR#/PCI1 SIOPCLK 7 8
12 MULT PCICLK1 5 6 CN14
VCC3 CB10 MULTSEL/PCI2 PCICLK2 3 4 X_8P4C-10P
104P 14 7 8 SIOPCLK
SIOPCLK 15
5494.28 PCICLK3 1 2
PCI3 RN86 5 PCICLK1 4879.14
PCI4 15 6 PCICLK1 18
13 17 3 4 PCICLK2
PCICLK2 18
4812.54
R184 PCI_GND PCI5 PCICLK3 4804.1
CLKSTOP#/PCI6 18 1 2 PCICLK3 18
4.7K USBCLK C256 X_10P
22 8P4R-33
R199 10K VTTGD# 48_VDD FS3 R273 47 USBCLK 1002.89 SIO_48M C170 X_10P
FS3/48MHz 20 USBCLK 14
CB24
R97 104P 19 21 FS2 R276 47 SIO_48M
SIO_48M 15
5668.7 SB14MHZ C251 X_10P
Q29 48_GND FS2/24_48MHz
VCORE
2N3904S 55 R251 22 SB14MHZ
SB14MHZ 13
2758.67 GUICLK C224 X_10P
220 REF_VDD FS0 R249 22 APICCLK 2758.25
FS0/REF0 1 APICCLK 12
CB16 56 VTTGD# R191 33 GUICLK
GUICLK 6
7616.74 APICCLK C248 X_10P
X_104P 2 VTT_GD#/REF1
REF_GND
C 23 3 X1 C241 22P C
CORE_VDD X1
CB21 X2 14M-32pf-HC49S-D
104P 24 4 X2 C239 22P
CORE_GND X2
SMBCLK1 27 25 R275 475RST
9,13,17,23 SMBCLK1 SCLK IREF CN11 X_8P4C-10P
SMBDATA1 28 26 R262 33 MDCLK4 1 2
9,13,17,23 SMBDATA1 SDATA PD#/RESET# FP_RST# 23,25
MDCLK#4 3 4
44 DCLK4 1 2 MDCLK4
MDCLK4 9
6585.86 MDCLK1 5 6
FB8 X_80_0805 VCC2.5B DDR0/SDR0 DCLK#4 MDCLK#4 6571.65 MDCLK#1
VCC2_5 34 DDR/SDR_VDD DDR#0/SDR1 43 3 4 MDCLK#4 9 7 8
DCLK1 5 6 MDCLK1
MDCLK1 9
6572.72
42 DCLK#1 7 8 MDCLK#1
MDCLK#1 9
6558.81
CP8 CB7 DDR1/SDR2 CN12 X_8P4C-10P
DDR#1/SDR3 41
104P RN67 X_8P4R-10 MDCLK5 1 2
X_COPPER 33 38 DCLK5 1 2 MDCLK5
MDCLK5 9
6534.08 MDCLK#5 3 4
CB12 CB14 DDR/SDR_GND DDR2/SDR4 DCLK#5 MDCLK#5 6559.35 MDCLK2
DDR#2/SDR5 37 3 4 MDCLK#5 9 5 6
X_104P X_104P DCLK2 5 6 MDCLK2
MDCLK2 9
6530.34 MDCLK#2 7 8
36 DCLK#2 7 8 MDCLK#2
MDCLK#2 9
6538.01
DDR3/SDR6
40 DDR/SDR_VDD DDR#3/SDR7 35
RN68 X_8P4R-10 CN13 X_8P4C-10P
DDR4/SDR8 32 DCLK0 1 2 MDCLK0
MDCLK0 9
6526.65 MDCLK0 1 2
CB6 31 DCLK#0 3 4 MDCLK#0
MDCLK#0 9
6527.7 MDCLK#0 3 4
104P DDR#4/SDR9 DCLK3 MDCLK3 6517.22 MDCLK3
5 6 MDCLK3 9 5 6
39 30 DCLK#3 7 8 MDCLK#3
MDCLK#3 9
6523.13 MDCLK#3 7 8
DDR/SDR_GND DDR5/SDR10
DDR#5/SDR11 29
RN69 X_8P4R-10
4709.51 7 DCLK_OUT 45 46 R207 33 DCLK_FB
DCLK_FB 7
8504.56 DCLK_FB C220 X_10P
B BUF_IN FB_OUT B
ICS950910
used only for EMI issue
Trace less 0.2"
DCLK4 MDCLK4
DCLK#4 MDCLK#4
DCLK1 MDCLK1
Shut Source Termination Resistors CLOCK STRAPPING RESISTORS DCLK#1 MDCLK#1
CPUCLK R192 49.9RST
CPUCLK# R193 49.9RST FS3 R259 10K VCC3V MULT R254 10K VCC3V DCLK5 MDCLK5
FS2 R260 10K DCLK#5 MDCLK#5
R274 X_10K R272 X_10K DCLK2 MDCLK2
DCLK#2 MDCLK#2
FS1 R268 10K
BSEL1 4
MULT Rr Iref Ioh Voh
Trace less 0.2" 49.9ohm for 50ohm M/B impedance DCLK0 MDCLK0
FS0 R250 10K
BSEL0 4,13
0 221 5.00mA 4*Iref 1.0V DCLK#0 MDCLK#0
DCLK3 MDCLK3
1 475 2.32mA 6*Iref 0.7V DCLK#3 MDCLK#3
A A
FS3 FS2 FS1 FS0 FSB (MHz)
1 1 0 0 100 MHz
1 1 0 1 133 MHz MSI
1
1
1
1
1
1
0
1
200
166
MHz
MHz
Micro-Star
Title
MODE R271 10K VCC3V
Clock Generator
SEL_CK408 R252 10K Size Document Number Rev
10B1
MS-6787
Date: Monday, February 09, 2004 Sheet 3 of 27
5 4 3 2 1
5 4 3 2 1
VIDPWRGD DC Specifications
Min Typ Max
VIL 0.3
VIH 0.9
CPU SIGNAL BLOCK
It must rout to the enable pin of PWM and CK-409.
VIDGD to Vccp delay time is from 1ms to 10ms.
CPUVID_GD 24
HA#[3..33] VIDGD rising time is 150ns.
6 HA#[3..33]
VID[0..5] 24
HA#33
HA#32
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
D D
CPU GTL REFERNCE VOLTAGE BLOCK
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID5
VID4
VID2
VID1
VID0
VID3
VCORE
AD26
AC26
AE25
AD2
AD3
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
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