Service Manuals, User Guides, Schematic Diagrams or docs for : Microstar MS-6788
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1
Cover Sheet 1
Block Diagram 2 MS(6788) Version 200
GPIO 3 Intel (R) Breeds Hill (GMCH) + ICH5 Chipset
Intel mPGA478B CPU - Signals 4 Intel Northwood mPGA478B Processor
Intel mPGA478B CPU - Power 5 CPU:
Intel Breeds Hill - Host Signals 6 Intel Northwood
Intel Breeds Hill - Memory Signals 7 System Chipset:
Intel Breeds Hill - AGP 8 Intel Breeds Hill - GMCH (North Bridge)
DDR DIMM 1,2 9 Intel ICH5 (South Bridge)
PCB Holes 10 On Board Chipset:
ICH5(1) 11 BIOS -- FWH EEPROM
ICH5(2) 12 AC'97 Codec -- ALC655
LPC Super I/O -- W83627THF
ICS952611 & FWH & FDD 13
LAN --RTL8100C/8110S
A
LPC I/O -W83627THF 14 CLOCK --ICS 952611 A
AC97 Audio 15
Main Memory:
AGP 4X/8X Slot & FAN 16
DDR * 3 (Max 3GB)
PCI Slots 1 & 2 & 3 17
Expansion Slots:
PCI Slots 4 & 5 18
PCI2.3 SLOT * 5
ATA33/66/100 IDE & Video Connectors 19
USB Connectors 20 ST PWM:
ACPI controller 21 Controller: ST L6710
ATX & Front Panel 22
VRM 10.0 FMB2 23
DLED BRACKET 24
VID Adjust 25
EMI parts 26
RTL8100C/8110S 27 MICRO-STAR INt'L CO., LTD.
MSI
LAN Connector 28 Title
COVER SHEET
Size Document Number Rev
10A
MS-6788
Date: Tuesday, November 25, 2003 Sheet 1 of 29
1
1
VRM 10
Intersil 6556 Intel mPAG478B Processor
Block Diagram
3-Phase PWM
FSB
4X/8X
AGP 1.5V
Connector
64bit DDR RTL8100C/8110S
Analog Channel 1 2 DDR
Video Springdale DIMM
Out 64bit DDR Modules
Channel 2
Link
HUB
UltraDMA 33/66/100
IDE Primary PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
PCI Slot 5
IDE Secondary
ICH5 PCI ADDR/DATA
USB Port 0
A A
USB Port 1
USB
USB Port 2 LPC Bus
USB Port 3
SATA
USB Port 4
LPC SIO
USB Port 5 Winbond
83627THF
USB Port 6
USB Port 7
AC'97 Link
Flash Keyboard Floopy Parallel Serial
AC'97 Codec
Mouse
MSI
MICRO-STAR INt'L CO., LTD.
Title
BLOCK DIAGRAM
Size Document Number Rev
MS-6788 10A
Date: Tuesday, November 25, 2003 Sheet 2 of 29
1
1
ICH5
GPIO Pin Type Function Power well PCI Config.
GPIO 0 I PREQ#B MAIN DEVICE MCP1 INT Pin REQ#/GNT# IDSEL CLOCK CLK GEN PIN OUT
GPIO 1 I PREQ#B MAIN PCI Slot 1 INTA# PCI_REQ#0 AD16 PCICLK0 13 (PCI_CLK0)
GPIO 2 I PIRQ#E MAIN INTB# PCI_GNT#0
GPIO 3 I PIRQ#F MAIN INTC#
GPIO 4 I PIRQ#G MAIN INTD#
GPIO 5 I PIRQ#H MAIN PCI Slot 2 INTB# PCI_REQ#1 AD17 PCICLK1 14 (PCI_CLK1)
GPIO 6 I GPI6 MAIN INTC# PCI_GNT#1
GPIO 7 I GPI7 MAIN INTD#
GPIO 8 I CSA_PME# RESUME INTA#
GPIO 9 I OC4# RESUME PCI Slot 3 INTC# PCI_REQ#2 AD18 PCICLK2 15 (PCI_CLK2)
GPIO 10 I OC5# RESUME INTD# PCI_GNT#2
GPIO 11 I SIO_SMI# RESUME INTA#
GPIO 12 I EXTSMI# RESUME INTB#
GPIO 13 I SIO_PME# RESUME PCI Slot 4 INTD# PCI_REQ#3 AD19 PCICLK3 16 (PCI_CLK3)
GPIO 14 I OC#6 RESUME INTA# PCI_GNT#3
GPIO 15 I OC#7 RESUME INTB#
GPIO 16 O PGNT#A MAIN INTC#
GPIO 17 O PGNT#B MAIN PCI Slot 5 INTB# PCI_REQ#4 AD21 PCICLK4 19 (PCI_CLK4)
GPIO 18 O GPO18 MAIN INTC# PCI_GNT#4
GPIO 19 O BIOS_WP# MAIN INTD#
GPIO 20 O GPO20 MAIN INTA#
GPIO 21 O GPO21 MAIN
GPIO 22 OD GPO22 MAIN
GPIO 23 O GPO23 MAIN
GPIO 24 I/O GPIO24 RESUME default output
GPIO 25 I/O LAN_DISABLE# RESUME default output
GPIO 27 I/O GPIO27 RESUME default output
A
* GPIO 28 I/O GPIO28 RESUME default output A
GPIO 32 I/O GPIO32 MAIN default output
GPIO 33 I/O GPIO33 MAIN default output DDR DIMM Config.
GPIO 34 I/O GPIO34 MAIN default output
DEVICE ADDRESS CLOCK
GPIO 40 I PREQ#4 MAIN
DIMM 1 1010000B MCLK_A0/MCLK_A0#
GPIO 41 I GPI41 MAIN
MCLK_A1/MCLK_A1#
GPIO 48 O PGNT#4 MAIN
MCLK_A2/MCLK_A2#
GPIO 49 OD CPUPWRGD MAIN
DIMM 2 1010001B MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#
FWH
GPIO Pin Type Function
GPI 0 I PD_DET
GPI 1 I SD_DET
* GPI 2 I Pull down through 1K ohms (unused)
GPI 3 I Pull down through 1K ohms (unused) PCI RESET DEVICE
* GPI 4 I Pull down through 1K ohms (unused) Signals Target
PCIRST#1 Springdale,LAN,FWH, Super I/O
PCIRST#2 PCI slot 1-3, AGP slot
HD_RST# Primary, Scondary IDE
MSI
MICRO-STAR INt'L CO., LTD.
Title
General Purpose Spec
Size Document Number Rev
10A
MS-6788
Date: Tuesday, November 25, 2003 Sheet 3 of 29
1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK VIDPWRGD DC Specifications CPU GTL REFERNCE VOLTAGE BLOCK
Min Typ Max
CPU_VIDGD VIL 0.3
6 HA#[3..31]
VIH 0.9
VID[0..5] 25
It must rout to the enable pin of PWM and CK-409.
HA#31
HA#29
HA#27
HA#26
HA#24
HA#22
HA#21
HA#19
HA#17
HA#16
HA#14
HA#12
HA#11
HA#30
HA#28
HA#25
HA#23
HA#20
HA#18
HA#15
HA#13
HA#10
VIDGD to Vccp delay time is from 1ms to 10ms. VCCP
HA#9
HA#7
HA#6
HA#4
HA#8
HA#5
HA#3
VID2
VID1
VID0
VID5
VID4
VID3
VIDGD rising time is 150ns.
D D
AD26
AC26
AE25
R100
AD2
AD3
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
T5
T4
T2
T1
200R1%
L2
L3
L6
CPU1A GTLREF 0.63*Vccp
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
ITP_CLK1
ITP_CLK0
VID5#
VID4#
VID3#
VID2#
VID1#
VID0#
DBR#
VCC_SENSE
VSS_SENSE
VIDPWRGD
R110
HDBI#0 E21 C152 169R1%
6 HDBI#[0..3] DBI0#
HDBI#1 G25 AA21 X7R C0.1U25Y X7R
HDBI#2 DBI1# GTLREF3
P26 AA6
HDBI#3 DBI2# GTLREF2 GTLREF
V21 F20 GTLREF 6
DBI3# GTLREF1 C80 C220P50N
F6
IERR# GTLREF0 X7R {VOLTAGE}
AC3
IERR# BPM#5
V6 AB4
MCERR# BPM5# BPM#4
12 FERR# B6 AA5
FERR# BPM4# BPM#3
12 STPCLK# Y4 Y6
STPCLK# BPM3# BPM#2
AA3 AC4
BINIT# BPM2# BPM#1
12,13 HINIT# W5 AB5
INIT# BPM1# BPM#0
AB2 AC6
RSP# BPM0#
H5 H3 HREQ#4
6 HDBSY# DBSY# REQ4# HREQ#[0..4] 6
H2 J3 HREQ#3
6 HDRDY#
J6
DRDY# REQ3#
J4 HREQ#2 CPU ITP BLOCK
6 HTRDY# TRDY# REQ2#
K5 HREQ#1
REQ1# HREQ#0
6 HADS# G1 J1
ADS# REQ0#
6 HLOCK# G4
LOCK# TESTHI12 R60 62R
6 HBNR# G2 AD25 VCCP
BNR# TESTHI12 TESTHI11 R99 62R
6 HIT# F3 A6
HIT# TESTHI11 ITP_TDI R71 150R
6 HITM# E3 Y3 VCCP
HITM# TESTHI10 R80 62R
6 HBPRI# D2 W4
BPRI# TESTHI9 ITP_TRST# R78 680R
6 HDEFER# E2 U6
DEFER# TESTHI8
AB22
C ITP_TDI TESTHI7 C
C1 AA20
ITP_TDO TDI TESTHI6 ITP_TMS R83 X_39.2R1%
D5 AC23 VCCP
ITP_TMS TDO TESTHI5 ITP_TDO R73 X_75R
F7 AC24
ITP_TRST# TMS TESTHI4
E6 AC20
ITP_TCK TRST# TESTHI3 ITP_TCK R74 27R
D4 AC21
TCK TESTHI2 TESTHI1 R77 62R
14 CPU_TMPA B3 AA2
THERMDA TESTHI1 TESTHI0 R68 62R
14 VTIN_GND C4 AD24
THERMTRIP# THERMDC TESTHI0
12 THERMTRIP# A2
THERMTRIP#
AF26 AF23 CPU_CLK# 13
PROCHOT# GND/SKTOCC# BCLK1#
6 PROCHOT# C3 AF22 CPU_CLK 13
PROCHOT# BCLK0#
12 IGNNE# B2
IGNNE# HRS#2
12 SMI# B5 F4 HRS#[0..2] 6
SMI# RS2# HRS#1
12 A20M# C6 G5
A20M# RS1# HRS#0
12 SLP# AB26 F1
SLP# RS0#
A22 V5
RESERVED0 AP1#
A7 AC1
RESERVED1 AP0# HBR#0
AE21 H6 HBR#0 6
RESERVED2 BR0#
AF24
RESERVED3 COMP1 R85 60.4R1%
AF25 P1
RESERVED4 COMP1 COMP0 R92 60.4R1%
L24
BOOT COMP0
23 BOOT AD1
BOOTSELECT
AE26 L25
OPTIMIZED/COMPAT# DP3# VCC_VID
K26 5,21 VCC_VID
DP2#
13 BSEL0 AD6 K25
BSEL0 DP1#
13 BSEL1 AD5 J26
BSEL1 DP0# R40
CPU_GD AB23 R5 1KR
12 CPU_GD PWRGOOD ADSTB1# HADSTB#1 6
L5 HADSTB#0 6
CPURST# ADSTB0# CPU_VIDGD
6 CPURST# AB25 W23 HDSTBP#3 6 Q12
RESET# DSTBP3#
P23 HDSTBP#2 6
B
HD#63 DSTBP2# N-MMBT3904_SOT23 B
6 HD#[0..63] AA24 J23 HDSTBP#1 6
HD#62 D63# DSTBP1# R812
AA22 F21 HDSTBP#0 6 VID_GD 21,23
HD#61 D62# DSTBP0#
AA25 W22 HDSTBN#3 6
HD#60 D61# DSTBN3# 1KR
Y21 R22 HDSTBN#2 6
HD#59 D60# DSTBN2#
Y24 K22 HDSTBN#1 6
HD#58 D59# DSTBN1#
Y23 E22 HDSTBN#0 6
HD#57 D58# DSTBN0#
W25
HD#56 D57#
Y26 E5 NMI 12
HD#55 D56# LINT1/NMI
W26 D1 INTR 12
HD#54 D55# LINT0/INTR
V24
D54#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
M26
M24
M23
M21
G26
G23
G22
U21
U23
U24
U26
R24
R25
R21
N25
N26
N23
N22
H25
H24
D26
H22
D25
D23
C26
H21
C24
C23
D22
C21
V22
V25
P24
P21
K23
E25
E24
B25
B24
A25
A23
B22
B21
T23
T22
T25
T26
F26
F24
F23
_ZIF-SOCKET478
L22
L21
J24
J21
{Priority}
HD#52
HD#51
HD#49
HD#47
HD#46
HD#44
HD#42
HD#41
HD#39
HD#37
HD#36
HD#34
HD#32
HD#31
HD#29
HD#27
HD#26
HD#24
HD#22
HD#21
HD#19
HD#17
HD#16
HD#14
HD#12
HD#11
HD#53
HD#50
HD#48
HD#45
HD#43
HD#40
HD#38
HD#35
HD#33
HD#30
HD#28
HD#25
HD#23
HD#20
HD#18
HD#15
HD#13
HD#10
HD#8
HD#5
HD#3
HD#0
HD#9
HD#7
HD#6
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