Service Manuals, User Guides, Schematic Diagrams or docs for : NEC _dataSheets uPD765_Data_Sheet_Dec78

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uPD765_Data_Sheet_Dec78


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                                                                                                                                          NEe
NEe Microcomputers, Inc.                                                                                                                 fLPD765


                                                   SINGLE/DOUBLE DENSITY
                                                   FLOPPY DISK CONTROLLER'


                        OESCRI PTION               The J.1PD765 is an LSI Floppy Disk Controller (FDC) Chip, which contains the circuitry and control
                                                   functions for interfacing a processor to 4 Floppy Disk Drives, It is capable of supporting either
                                                   IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including
                                                   double sided recording. The J.1PD765 provides control signals which simplify the design of an
                                                   external phase locked loop, and write precompensation circuitry. The FDC simplifies and handles
                                                   most of the burdens associated with implementing a Floppy Disk Interface.
                                                   Hand-shaking signals are provided in the J.1PD765 which make DMA operation easy to incorporate
                                                   with the aid of an external DMA Controller chip, such as the J.1PD8257. The FDC will operate in
                                                   either DMA or Non-DMA mode. In the Non-DMA mode, the FDC generates interrupts to the
                                                   processor every time a data byte is available. In the DMA mode, the processor need only load the
                                                   command into the FDC and all data transfers occur under control of the J.1PD765 and DMA
                                                   controller.
                                                   There are 15 separate commands which the J.1PD765 will execute. Each of these commands requ ire
                                                   multiple 8-bit bytes to fully specify the operation which the processor wishes the F DC to perform.
                                                   The following commands are available:
                                                             Read Data                Scan High or Equal     Write Deleted Data
                                                             Read ID                  Scan Low or Equal      Seek
                                                             Read Deleted Data        Specify                Recalibrate (Restore to Track 0)
                                                             Read a Track             Write Data             Sense I nterrupt Status
                                                             Scan Equal               Format a Track         Sense Drive Status

                             FEATURES              Address mark detection circuitry is internal to the FDC which simplifies the phase locked loop and
                                                   read electronics. The track stepping rate, head load time, and head unload time may be programmed
                                                   by the user. The J.1PD765 offers many additional features such as multiple sector transfers in both
                                                   read and write with a single command, and full IBM compatibil ity in both single and double
                                                   density modes.
                                                   



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