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AMD GeodeTM Solutions
External NAND Flash Memory
Circuit on IDE Interface

1.0       Scope
This application note describes an external NAND Flash          Additional decode circuitry is required to have either a hard
module and explains how to connect it to an AMD GeodeTM         disk and a NAND device, or multiple NAND devices on the
Solutions based system via its IDE interface. The GeodeTM       same IDE channel. The decode could exist as a GPIO sig-
CS5535 and CS5536 companion devices both feature                nal and its complement to gate the CS0# signals to the
NAND Flash controllers, however, this Flash on IDE solu-        hard disk and the NAND device. Figure 2-2 shows a exam-
tion yields better performance. The NAND Flash module in        ple of how this could be realized.
this application is used by the system for the operating sys-                         VCC
tem. The NAND device is not used for BIOS storage.
Note:   This is revision B of this document. The change
        from revision A (dated July 2005) is the addition of
        the second sentence in the scope for clarification.           GPIOx                                    CS0# to IDE
                                                                   IDE_CS0#                                    Hard-disk CS0#


2.0       Discussion                                                                                           CS0# to
The NAND flash module connects to the AMD Geode                                                                NAND CE#
device's IDE interface to provide higher data throughput
than can be achieved using an ISA bus interface. Figure 2-            Figure 2-2. Additional Decode Circuitry
1 shows a typical application that is functional in a system
where the NAND device is the only device on its IDE chan-       The addressing for the various ports on the NAND device
nel. Two possible architectures that support this scheme        are dependant upon which IDE channel the NAND device
are:                                                            is connected to. Table 2-1 lists the NAND device ports and

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