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AMD GeodeTM GX1 Processor
Silicon Revision 8.1.1
Specification Update
1.0 Scope
This document discusses known issues of the AMD date, etc. However, the "A" in the 5th character is constant.
GeodeTM GX1 processor, silicon revision 8.1.1. Table 1-1 Software can detect this revision by reading the DIR1 Con-
provides a summary of the issues. A detailed description of figuration register (see Configuration registers in the GX1
each issue, its impact, and a recommended resolution/fix data book). The value read from DIR1 is 81h for silicon
follow. revision 8.1.1.
To determine the silicon revision of the device, printed on Silicon errata are tracked separately. This document per-
the chip (bottom-side of SPGA, top-side of EBGA) is the lot tains to silicon revision 8.1.1 only.
code number. The lot code number for silicon revision 8.1.1
Note: This is revision 8.1 of this document. The change
is a 10-digit number with an "A" in the 5th character (e.g.,
from revision 8.0 (dated May 2002) is in format
V8SKA040AG). Note that the other characters of the lot
only. No technical changes.
code number may change depending upon lot number,
Table 1-1. Errata Summary
Issue #1 Description
1 Incorrect CURRENT_IP field in SMI header
2 RSM truncates page-granular CS limit
3 SDRAM CAS latency of 1 not supported
4 VIH change from 2.0V to 2.1V on FLT# input
5 PCI AD bus floats too early on some target terminated cycles, not PCI 2.1 compliant
6 Memory writes in SMI handler could have A20 in their address cleared
7 Double fault handled as general protection fault
8 Call ESP does not work
9 PCI signal SERR# asserts for two clocks, not one
10 PCI signal LOCK# ignored
11 PCI signal PERR# is floated instead of driven high on deassertion
12 PCI REQs must not go active during reset
13 CALL at beginning of Code Segment Call causes General Protection Fault
14 Self modifying code can cause PF
15 Time Stamp Counter stops during Suspend
17 WORD access to Port 23; Port 24 half of access goes off chip
19 Thermal diode does not work
20 PCI Master Latency Timer is broken
21 Data setup to PCLK does not meet specification
22 Data setup to VID_CLK does not meet specification
23 Video port limited to 133 MHz
24 Behavior of EFLAGS during INTR handling is not as expected
25 Graphics resolution of 1280x1024x16 is not supported
26 I/O write interlock
27 Time Stamp Counter rollover
1. Issue numbers may not be sequential since issues are omitted once they are resolved.
Revision 8.1 - January 2004 - Confidential 1
Specification Update
Revision 8.1 - January 2004 - Confidential
2.0 Issues
1. Incorrect CURRENT_IP field in SMI header 5. PCI AD bus floats too early on some target termi-
nated cycles, not PCI 2.1 compliant
Description: When two SMIs overlap, the
CURRENT_IP field of the SMI header for the second Description: The problem cycles occur when the
SMI is wrong (contains EFLAGS instead of processor is the target and the cycle is a read. The
CURRENT_IP). AD bus goes TRI-STATE when TRDY# goes inactive.
The processor should TRI-STATE the AD bus when
Implications: None. The CURRENT_IP field is not
IRDY# goes inactive. However, under certain target
normally used in SMM code, so this has typically not
abort conditions, IRDY# stays active longer then
been a problem.
TRDY#, leaving the AD bus undriven for a few PCI
Resolution: If required, there is code available that clocks.
allows the SMM handler to calculate the
Implications: This breaks PCI compliance, however,
CURRENT_IP field.
there are no functional problems with this issue.
2. RSM (Resume from SMM) truncates page-gran- Resolution: None.
ular CS (Code Segment) limit
6. Memory writes in SMI handler could have A20 in
Description: When RSM loads the CS segment limit
their address cleared
from the SMI header, it truncates it to 20 bits. If the
CS segment was page-granular, it shifts left 12 bits Description: If a memory write cycle occurs that has
and the upper 12 bits of the original limit are lost. A20 set near an RSM instruction, the write may be
posted and delayed. When the write cycle is actually
Implications: The system executes code at the
executed, the Force A20 logic is applied.
wrong location after an RSM to a page-granular CS
segment. Implications: This can cause the data to go to the
wrong address. Unpredictable system behavior can
Resolution: There is a software workaround for this
result.
issue that is implemented in the processor's SMI
handlers. PAGE_GRAN (bit 31 of the CS segment Resolution: Avoid memory write cycles that have
field) is tested in the middle of the handler. If set, the A20 set near the RSM, or execute an I/O cycle before
limit field in the SMI header is shifted right by 12 bits. the RSM forcing any posted write to execute before
If not set, nothing is done. the RSM executes.
3. SDRAM CAS latency of 1 not supported 7. Double fault handled as general protection fault
Description: When CAS latency is set to 1, the Description: A CLI is pending, causing a CPU privi-
memory controller does not pick up read data prop- lege level exception. The trap gate points to a "not
erly. present" code segment. Both of these faults are
contributory class exceptions and a double fault
Implications: CAS latency of 1 cannot be used.
should be taken.
Resolution: CAS latency of 1 is not supported. The
Implications: A double fault is not taken, however,
impact of this is minor, as there are very few (if any)
the "not present" fault is taken. This is not a functional
SDRAMs that support this setting.
issue. This fault condition is a result of a coding error.
A fault is taken; just not the correct fault.
4. VIH change from 2.0V to 2.1V on FLT# input
Resolution: None required.
Description: The Voltage Input High (VIH) on the
FLT# input has been changed from 2.0V to 2.1V.
Implications: None. In most systems, FLT# is
normally unused and pulled to VCC3.
Resolution: None.
2 AMD GeodeTM GX1 Processor Silicon Revision 8.1.1
Specification Update
Revision 8.1 - January 2004 - Confidential
8. Call ESP does not work 13. CALL at beginning of Code Segment Call causes
General Protection Fault
Description: Call ESP instruction is broken.
Description: A segment exists that has a base
Implications: This instruction exists because of the
address that is not 16-byte aligned and the limit of
way the call register instruction is created. This
that segment is at the maximum (FFFFFFFFh). A call
instruction is never used. Using this call and
instruction is made to the beginning of the segment,
managing the stack becomes extremely difficult if not
that happens to be in the middle of the 16-byte line
impossible. Do not use this instruction.
fetch. The limit checking hardware assumes that the
Resolution: None. limit has been crossed because the line fetch
contains both the beginning and the end of the
segment. The hardware is unable to discern that the
9. PCI signal SERR# asserts for two clocks, not one
actual code execution does not cross the limit,
Description: SERR# is asserted for two clocks. hence, causing a general protection fault to occur.
Implications: This breaks PCI compliance. Fault Implications: This is a real coding hazard, however,
tolerant systems are the only systems affected by coding practices are such that when a maximum
this issue. segment is created, the base is zero (which is 16-
byte aligned).
Resolution: None.
Resolution: None.
10. PCI signal LOCK# ignored
14. Self modifying code can cause PF
Description: The processor ignores the LOCK#
signal when PCI bus masters assert LOCK# during a Description: A memory write is generated due to an
bus transaction. STOS instruction that is on a page boundary, which
modifies the STOS instruction. This is followed by a
Implications: This breaks PCI compliance.
JCC instruction that takes the IP back to where the
Resolution: None. STOS instruction was. The refetch occurs but the
address of the refetch is wrong.
11. PCI signal PERR# is floated instead of driven Implications: Self modifying code that executes as
high on deassertion described fails.
Description: PERR# is floated instead of driven high Resolution: None.
and then set to TRI-STATE.
Implications: This breaks PCI compliance. If imple- 15. Time Stamp Counter stops during Suspend
mented in a system, a strong pull-up should be used
Description: When the processor is in Suspend due
on this signal.
to SUSP#/SUSPA# or in HALT with the "Suspend on
Resolution: None. Halt" bit set, the Time Stamp Counter stops.
Implications: This is different from other CPUs.
12. PCI REQs must not go active during reset
Resolution: None.
Description: If a PCI REQ# goes active during reset,
the processor's arbiter may not function correctly
17. WORD access to Port 23; Port 24 half of access
after reset goes inactive.
goes off chip
Implications: None as long as the PCI REQ# is
Description: Executing a WORD I/O cycle to Port 23
pulled up during reset.
is a misaligned cycle that the processor converts into
Resolution: None. two BYTE cycles. When MAPEN = 1 (Index C3h[4]),
one cycle goes to Port 23 and the other to Port 24.
The Port 23 access does not go off chip since that is
a CPU I/O port, however, the Port 24 cycle does go
off chip.
Implications: None. There is typically nothing at Port
24.
Resolution: Access Port 23 using byte wide I/O
instructions.
AMD GeodeTM GX1 Processor Silicon Revision 8.1.1 3
Specification Update
Revision 8.1 - January 2004 - Confidential
19. Thermal diode does not work 23 Video port limited to 133 MHz
Description: The thermal diode at pins E24 and D26 Description: There is currently no I/O companion
of the EBGA package and F36 and E37 of the SPGA solution that supports 150 MHz on the video port.
package do not work. Treat these signals as no
Implications: VID_CLK is created by dividing the
connects.
core frequency by 2 or 4. With this limitation and a
Implications: The thermal diode cannot be used. core frequency of 300 MHz, VID_CLK can only be
divided by 4. With VID_CLK limited to 75 MHz, the
Resolution: None. Do not use this feature.
video window cannot be used if the graphics resolu-
tion is 1280x1024x85 Hz. 1280x1024x75 Hz and
20. PCI Master Latency Timer is broken lower function correctly.
Description: PCI register 0Dh, the Master Latency Resolution: None.
Timer, is broken. Setting this register to any value
other then 00h results in a system hang.
24. Behavior of EFLAGS during INTR handling is not
Implications: This breaks PCI compliance, however, as expected.
the Master Latency Timer is typically not used.
Description: If an IRQ occurs during EFLAGS style
Resolution: None. Do not use this feature. CPU ID support detection, bit 22 gets cleared. This is
different from an Intel CPU.
21. Data setup to PCLK does not meet specification Implications: Possible compatibility problems.
Description: Symbol t4 in Table 6-19 (Video Inter- Resolution: Disable IRQs during manipulation of
face Signals) in the GX1 data book is out of specifica- upper bits in EFLAGS.
tion. The timing of t4 is 5 ns, not 3.8 ns.
Implications: PCLK is limited to 135 MHz instead of 25. Graphics resolution of 1280x1024x16 is not
157 MHz. This limits maximum resolution to supported
1280x1024x75 Hz instead of 1280x1024x85 Hz.
Description: If the horizontal resolution is greater
Resolution: None. than 1024, the bits per pixel is limited to 8 instead of
16.
22. Data setup to VID_CLK does not meet specifica- Implications: The standard resolution of
tion 1280x1024x16 is not supported.
Description: Symbol t8 in Table 6-19 (Video Inter- Resolution: None.
face Signals) in the GX1 data book is out of specifica-
tion. The timing of t8 is 5 ns, not 3.8 ns.
Implications: VID_CLK is limited to 133 MHz (266/2)
instead of 150 MHz (300/2). VID_CLK is created by
dividing the core frequency by 2 or 4. With this limita-
tion and a core frequency of 300 MHz, VID_CLK can
only be divided by 4. With VID_CLK limited to 75
MHz, the video window cannot be used if the
graphics resolution is higher than 1024x768x85 Hz.
Resolution: None.
4 AMD GeodeTM GX1 Processor Silicon Revision 8.1.1
Specification Update
Revision 8.1 - January 2004 - Confidential
26 I/O write interlock 27 Time Stamp Counter rollover
Description: I/O writes are non-postable instruc- Description: The upper 32 bits of the Time Stamp
tions. Code execution is not supposed to continue Counter (TSC) increment three core clocks before
until the I/O write is completed. An I/O write instruc- the lower 32 bits rollover. If the TSC is read and EAX
tion that is executed on the PCI bus can be retried in is FFFFFFFDh, FFFFFFFEh, or FFFFFFFFh, then
a process called delayed transaction. This allows EDX will have incremented.
external PCI bus masters to gain control of the bus,
Implications: The TSC cannot be read reliably.
even though a long cycle is in progress to a slow
device, such as ISA bus devices. If a bus master Resolution: (1) Use the TSC as a 32 bit counter. (2)
gains control of the PCI bus during a delayed I/O When the TSC is read and EAX equals FFFFFFFD,
write and transfers data, the CPU core is signaled FFFFFFFEh, or FFFFFFFFh; then decrement the
that the delayed I/O write has completed. This allows EDX value by 1.
the CPU core to continue inadvertently.
Implications: The vast majority of I/O writes are not
affected by this issue, because they do not care if
code continues to execute even though they have not
completed. However, in extremely rare instances,
unexpected system behavior can result.
Resolution: If a critical I/O write exists, execute a
non-critical I/O read immediately after the I/O write.
AMD GeodeTM GX1 Processor Silicon Revision 8.1.1 5
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