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AMD GeodeTM GX1 Processor
Flash Memory Implementation
Options and Applications

1.0       Scope
This application note describes two methods of paged flash      2.1       Hardware Implementation
disk design for the AMD GeodeTM GX1 processor. The two
reference designs are Paged Flash Disk Using Memory             2.1.1     Memory Decode Design: Hardware
Decode and Paged Flash Disk Using the General Purpose                     Implementation
Chip Select. The purpose of this document is to explain the
                                                                The programmable logic device, the Atmel ATF22V10, is
hardware and software implementation for these two
                                                                used to decode a memory range window for accessing the
designs. Once the system designer understands the imple-
                                                                flash. As ISA bus signals SMEMR# and SMEMW# are only
mentation, these designs can be easily modified to use dif-
                                                                active when the memory range is below 1 MB, a full
ferent hardware if desired.
                                                                decode of all the ISA address lines is not necessary and
Note:   This is revision 1.1 of this document. The change       only ISA address lines SA[19:13] are used to decode the
        from revision 1.0 (dated December 2000) is in for-      memory range. The Programmable Logic Device (PLD)
        mat only. No technical changes.                         activates one of the eight flash device chip selects when a
                                                                memory access between C8000h and C9FFFh occurs,
                                                                meaning that at any one time, only an 8 KB region in one of
2.0       Discussion                                            the flash devices is available. To access another region,
                                                                there must be a mechanism for switching to either another
The design titled Paged Flash Disk Using Memory Decode
                                                                flash device or another 8 KB region in the flash device. The
includes eight flash devices, two latches, two NAND gates,
                                                                two transparent latches (74LCX573) and other logic blocks
and a programmable logic device (see attached sche-
                                                                within the PLD together perform this function. The PLD
matic). Once the software development is done, these flash
                                                                also decodes the memory addresses CA000h and
devices look like a 16 MB hard drive to a system using
                                                                CA001h. When a memory write occurs to CA000h, the
either DOS or Microsoft

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