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AMD GeodeTM Solutions
Integrated Processors, Companion
Devices, and System Platforms
October 2003
NOTICE
Advanced Micro Devices, Inc. ("AMD") has purchased the Information Appliance business unit of National Semiconductor Corporation ("National"), which consisted
primarily of the GeodeTM family of microprocessor products and related support products (GX1, GX2, CS5530A, CS5535, CS1301, CS1311, SC1100, SC1200,
SC1201, SC2100, SC2200, SC3200, XpressROMTM and XpressLoaderTM software, collectively, the "IA Products"). This business unit is now being operated by
AMD's PCS Division.
During a transitional period, AMD will continue to use and distribute IA Product technical and marketing documents originally produced by National in hard copy, pdf,
html or other electronic format.
Notwithstanding the appearance in this document of the National trade names, National trademarks, and National copyrights or other proprietary notices, AMD is the
seller of the IA Products described in this document, the owner of the content contained in this document, and the source/publisher of this document.
5 4 3 2 1
TABLE OF CONTENTS:
PAGE CONTENTS NOTES
P01 COVER PAGE 1
P02 COVER PAGE 2
P03 SC3200_01
P04 SC3200_02
P05 SC3200_03
D P06 SC3200_04 D
SC3200 TEPBGA Reference Schematic Rev 1.0 P07
P08
LVDS_TFT
SODIMM
P09 BOOT ROM & DOC
-TFT and IDE supported. P10 USB
-Parallel port not available from SC3200 P11
P12
COMPACT FLASH & SERIAL PORT
PRI AND SEC IDE
5
5
P13 SINGLE IDE & SERIAL 5
P14 ETHERNET
Design Notes: P15 STANDARD PCI SLOT 6
P16 MINI PCI SLOT 6
1) This design features the SC3200 in the TEPBGA package. Please read the SC3200 P17 AUDIO
Data sheet, and Errata document for the particular revision of silicon to be P18 SMART CARD
P19 LPC SUPER I/O, SERIAL, PARALLEL,
used. Certain parts of this schematic may need to be changed to accommodate FLOPPY PORTS
P20 CRT
work-arounds for issues with a particular silicon revision. P21 VIP
2) PCB Layout notes are included with this schematic in various places. However, P22 SYSTEM POWER
use the SC3200 Layout Guidelines for proper PCB layout.
C C
3) No board has been built from this schematic.
4) Not all sections of this design may be appropriate for a particular
application.
5) It is not recommended that both CompactFlash and IDE be used in the same
design. CompactFlash, Dual IDE ports, and a Single IDE port are shown on separate
sheets. The designer should choose one of the three sheets to use in a design.
6) It is not recommended that both a standard PCI slot and a Mini-PCI slot be
used in the same design. These are shown on separate sheets. The designer should
choose one or the other sheets to use in a design.
7) Please read the "Important Notice" below.
8) Be sure to check the IA Developers Web Site often to get updated schematics or
a schematic errata document.
B
9) The pin properties on part symbols may need to be changed to support a B
particular application.
IMPORTANT NOTICE
1. This document may not reflect the most recent changes in board development and debug. Any developer intending to
use this schematic as a reference should contact their local Field Applications Engineer, Regional Sales Office, or
Program Manager for schematic updates, design recommendations, and PCB layout guidelines. National also
recommends a design review of both the schematic diagram and PCB layout before considering production.
2. National reserves the right to change designs or specifications without notice. Customers are advised to obtain the
A A
latest versions of product specifications, which should be considered in evaluating a product's appropriateness for a
particular use.
*NATIONAL CONFIDENTIAL*
3. National makes no warranties, expressed or implied, for merchantability or fitness for a particular application. In no event National Semiconductor
shall National be liable for any indirect, special, incidental or consequential damages as a result of the performance, or 1351 S Sunset St.
failure to perform, of any National product or documentation. Longmont, CO 80501
Title
SC3200 REFERENCE SCHEMATICS
Size Document Number Rev
C COVER PAGE 1 1.0
Date: Thursday, May 01, 2003 Sheet 1 of 21
5 4 3 2 1
5 4 3 2 1
LAST USED REFERENCES
Z53
U29
R160
TP26
C307
Revision History: Q7
Y4
FB22
D Rev Date Change Log D
----- ------------ ------------------------------------------------------------------------------------- JP3
BT1
1.0 04-25-03 Initial release BH1
SW1
D20
JLCD1
J20
JCF1
T2
PCI1
X1
L8
FS1
JS2
RP11
JDCIN1
F1
C C
B B
A A
*NATIONAL CONFIDENTIAL*
National Semiconductor
1351 S Sunset St.
Longmont, CO 80501
Title
SC3200 REFERENCE SCHEMATICS
Size Document Number Rev
C COVER PAGE 2 1.0
Date: Thursday, May 01, 2003 Sheet 2 of 21
5 4 3 2 1
5 4 3 2 1
SC3200 INTERFACES: PCI/SUB-ISA, LPC, AUDIO, DOC, PCI CLOCKS; STRAP VCC3.3V
PCI BUS PULL-UP'S
OPTIONS, PCI BUS PULL-UPS 8
7
1
2
INTAX
INTBX
VCC3.3V 6 3 IOCHRDY_GPIO19_INTC#
5 4
2.2K-16P8R/4016
PCI CLOCK DISTRIBUTION Z1 10K-8P4R/3216
DESIGN NOTE: If two or less PCI clocks are needed and
Z3 1 8 FRAME#
10
11
12
13
14
15
16
the DP83815, Ethernet Controller, is not used for a
9
PCICLK0 2 7 LOCK#
LOCK# <15>
DESIGN NOTE: See To Straps design, the ICS 552-01B may be removed. See the " PCI 3 6 PERR#
PCICLK1 Clock Considerations" appnote for more details. 4 5 SERR#
D
Rev D2 device
errata, issue #4.37.
U1A
SC3200 VCC3.3V
U2
Z2 10K-8P4R/3216
D
REQ0#
8
7
6
5
4
3
2
1
4 3 1 8
VDD DC REQ1#
DESIGN NOTE: PCICLK length must 5
VDD DC
2 2 7
LPC BUS PCI ONLY 15 7 R1 1 33 ohm 3 6
LAD0_GPIO32 PCICLK match PCICLKBUF_X length. VDD QA1 R2 1 33 ohm
PCICLKBUF_0 <14>
<19> LAD0_GPIO32 M28 LAD0_GPIO32 PCICLK A7 16 8 PCICLKBUF_1 <19> 4 5
LAD1_GPIO33 R3 10 ohm VDD QA2
<19> LAD1_GPIO33 L31 LAD1_GPIO33 1 9
LAD2_GPIO34 PCICLK0 INA QA3 Z4 10K-8P4R/3216
<19> LAD2_GPIO34 L30 LAD2_GPIO34 PCICLK0 A4 1 19 10
LAD3_GPIO35 INB QA4 R4 1 33 ohm
<19> LAD3_GPIO35 L29 11 12 PCICLKBUF_2 <15,16>
LAD3_GPIO35 PCICLK1 S1 QB1
PCICLK1 D6 20 13 1 8
LDRQ#_GPIO36 S0 QB2
<19> LDRQ#_GPIO36 L28 6 17 2 7
LFRAME#_GPIO37 LDRQ_GPIO36 INTAX GND QB3 R5 1 33 ohm DEVSEL#_BHE#
<19> LFRAME#_GPIO37 K31 D26 INTAX <15,16,20> 14 18 3 6
LFRAME_GPIO37 INTA* INTBX GND QB4 PCI_PME#
TP1 TEST PAD T LPCPD#_GPIO38 K28 C26 INTBX <14,15,16,20> 4 5 PCI_PME# <15,16>
SERIRQ_GPIO39 LPCPD_GPIO38 INTB*
<19> SERIRQ_GPIO39 J31 ICS552-01B
SERIRQ_GPIO39 FRAME# Z5 10K-8P4R/3216
FRAME* D8 FRAME# <14,15,16>
H3 LOCK#
LOCK* LOCK# <15>
H2 PERR# 1 8 SD0
USB PERR* PERR# <14,15,16>
H1 SERR# 2 7 SD1
SERR* SERR# <14,15,16>
USB_PWREN AH1 DESIGN NOTE: Locate R-PACKS so that 3 6 SD2
<10> USB_PWREN POWEREN
USB_OVCUR# AF4 B5 REQ0# 4 5 SD3
<10> USB_OVCUR# OVERCUR* REQ0* GNT0#
REQ0# <14> no stubs are made on the PCI bus.
GNT0* C5 GNT0# <14>
USBD1+ A28 Z8 75-16P8R/4016 Z6 10K-8P4R/3216
<10> USBD1+ DPPORT1
USBD1- A29 A5 REQ1# Z10 75-16P8R/4016
<10> USBD1- DMPORT1 REQ1* REQ1# <15,16>
C6 GNT1# Z12 75-16P8R/4016 1 8 SD4
GNT1* GNT1# <15,16> AD[0..31] <14,15,16>
USBD2+ B27 SA[0..18] 2 7 SD5
<10> USBD2+ DPPORT2 PCI / SUB-ISA SA[0..18] <9>
USBD2- B28 3 6 SD6
<10> USBD2- DMPORT2 AD0 AD0
U1 16 1 SA0 4 5 SD7
USBD3+ ADD00_A0 AD1 AD1 SA1
<10> USBD3+ A26
DPPORT3 ADD01_A1 P3 DESIGN NOTE: If more 15 2
USBD3- A27 U3 AD2 AD2 14 3 SA2 Z7 10K-8P4R/3216
<10> USBD3- DMPORT3 ADD02_A2
N1 AD3 REQ/GNT pairs are AD3 13 4 SA3
ADD03_A3 AD4 needed, see the AD4 SA4 CBE0#_D8
ADD04_A4 P1 12 5 1 8
N3 AD5 "Request/Grant pair AD5 11 6 SA5 2 7 CBE1#_D9
ADD05_A5 AD6 AD6 SA6 CBE2#_D10
N2 10 7 3 6
AUDIO INTERFACE ADD06_A6
M2 AD7 expansion" appnote AD7 9 8 SA7 4 5 CBE3#_D11
BITCLK ADD07_A7 AD8 AD8 SA8
<17> BITCLK U30 M4 16 1
SDATAOUT BITCLK ADD08_A8 AD9 AD9 SA9 Z9 10K-8P4R/3216
<17> SDATAOUT P29
SDATAOUT_TFTPRST ADD09_A9 L2 15 2 DESIGN NOTE: See PCI-ISA
SDATAIN1 U31 L3 AD10 AD10 14 3 SA10
<17> SDATAIN1
SDATAIN2 SDATAIN1 ADD10_A10 AD11 AD11 SA11
Mid-Termination AppNote PAR_D12
C
TP2 TEST PAD T AL8 K1 13 4 1 8 C
SDATAIN2 ADD11_A11 AD12 AD12 SA12 TRDY#_D13
ADD12_A12 L4 12 5 2 7
SYNC P30 J1 AD13 AD13 11 6 SA13 3 6 IRDY#_D14
<17> SYNC SYNC_CLKSEL3 ADD13_A13 AD14 AD14
K4 10 7 SA14 4 5 STOP#_D15
AC97CLK ADD14_A14 AD15 AD15 SA15
<17> AC97CLK P31 J3 9 8
AC97CLK ADD15_A15 AD16 AD16 SA16 Z11 10K-8P4R/3216
ADD16_A16 E1 16 1
AC97RST# U29 F4 AD17 AD17 15 2 SA17
<17> AC97RST# AC97RST* ADD17_A17 AD18 AD18
PCBEEP_GPIO16 V31 E3 14 3 SA18 1 8 WR#
<17> PCBEEP_GPIO16 PCBEEP_GPIO16 ADD18_A18 AD19 AD19
E2 13 4 2 7 RD#
ADD19_A19 AD20 AD20 ROMCS#
ADD20_A20 D3 12 5 DESIGN NOTE: SA[19:23] have no connection in this 3 6
D1 AD21 AD21 11 6 4 5
SERIAL 1 ADD21_A21 AD22 AD22 schematic. If they are needed, make sure mid-termination GPIO20_DOCCS# <6,9>
ADD22_A22 D2 10 7
SIN1 AG2 B6 AD23 AD23 9 8 rules are applied. See PCI-ISA Mid-Termination AppNote. Z13 10K-8P4R/3216
<18> SIN1 SOUT1 SIN1 ADD23_A23
<18> SOUT1 AF3
DTR1X_GPIO18_BOUT1 SOUT1_CLKSEL1 Z15 75-16P8R/4016 SD[0..7] LAN_PME#
TP3 TEST PAD T AG1 SD[0..7] <9> 1 8 LAN_PME# <6,14>
DTR1X_GPIO18_BOUT1 AD24 AD24
AD24_D0 C2 16 1 SD0 2 7
C4 AD25 AD25 15 2 SD1 3 6
SERIAL 2 AD25_D1 AD26 AD26
AD26_D2 C1 14 3 SD2 4 5
SIN2_SDTEST3 E28 D4 AD27 AD27 13 4 SD3
<11,13> SIN2 SIN2_SDTEST3 AD27_D3 AD28 AD28
SOUT2 D29 B4 12 5 SD4 Z14 10K-8P4R/3216
<11,13> SOUT2 SOUT2_CLKSEL2 AD28_D4 AD29 AD29
AD29_D5 B3 11 6 SD5
RTS2#_GPIO07_IDEDACK1# C30 A3 AD30 AD[0..31] AD30 10 7 SD6
<11,12,13> RTS2#_GPIO07_IDEDACK1# CTS2#_GPIO08_IDEDREQ1 RTS2*_GPIO07_IDEDACK1* AD23_D6 AD31 AD31
<11,12,13> CTS2#_GPIO08_IDEDREQ1 C31 D5 9 8 SD7
CTS2*_GPIO08_IDEDRQ1 AD31_D7
<7,11,12,13> DTR2#_GPIO06_BOUT2_IDEIOR1#
<11,12,13> RI2#_GPIO11_IRQ15
DTR2#_GPIO06_BOUT2_IDEIOR1#
RI2#_GPIO11_IRQ15
DCD2#_GPIO09_IDEIOW1#
D28
AJ8
DTR2*_GPIO06_BOUT2_IDEIOR1*
RI2*_GPIO11_IRQ15 CBE0*_D8 L1 CBE0#_D8
CBE0#_D8 <14,15,16>
SC3200 STRAP SELECTIONS
C28 J2 CBE1#_D9
<11,12,13> DCD2#_GPIO09_IDEIOW1# DSR2#_GPIO10_IDEIORDY1 DCD2*_GPIO09_IDEIOW1* CBE1*_D9 CBE1#_D9 <14,15,16>
B29 F3 CBE2#_D10
<11,12,13> DSR2#_GPIO10_IDEIORDY1 DSR2*_GPIO10_IDEIORDY1 CBE2*_D10 CBE2#_D10 <14,15,16>
H4 CBE3#_D11 DESIGN NOTE: SD[15:8] and BHE# have no STRAP FUNCTION VCC3.3V
CBE3*_D11 CBE3#_D11 <14,15,16>
PAR_D12
connection in this schematic. If they are
PAR_D12 J4 PAR_D12 <14,15,16>
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