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Keysight Technologies
W1717 SystemVue
Hardware Design Kit
Data Sheet
From Algorithm
to Implementation
of Digital Signal
Processing Systems
Overview
The W1717 SystemVue Hardware Design Kit (HDK) is a hardware design flow personality that adds
onto the core W1461 SystemVue core environment to accelerate the design and verification of digital
signal processing (DSP) algorithms in communications and aerospace defense systems. It allows
system architects and algorithm developers to create baseband models quickly and validate their
performance at the system-level against RF models, test equipment, Standards references, and other
signals and conditions.
The W1717 HDK enables a model-based design approach to FPGA rapid prototyping and integrates
easily into mainstream design and verification flows. It includes a synthesizable fixed-point model
library, and offers a rich set of example designs, ranging from basic filters to realistic communications
physical layer design.
03 Keysight W1717 SystemVue Hardware Design Kit Data Sheet
Key Features
Design and Verification Productivity
System-level modelers and verification engineers can take
advantage of SystemVue's comprehensive integration
into hardware design and verification flows. A fixed-point
simulation library predicts hardware-like effects without
committing to a targeted implementation, and generates
synthesizable, hierarchical, RTL-level Verilog and VHDL
that is bit-true and cycle accurate. This provides a path to
implementation and creates a verification wrapper for poly-
morphic model-based design flows moving from algorithm
to fixed point to RTL and to instantiated hardware. The
ability to co-simulate with external hardware description
language (HDL) simulators or real hardware is included
free with the SystemVue core environment.
Figure 2. The HDK provides the fastest hardware design flow, enabling high performance and high
productivity
04 Keysight W1717 SystemVue Hardware Design Kit Data Sheet
Fixed Point Design
Mapping signal-processing algorithms to dedicated hardware with The fixed-to-float and float-to-fixed conversion parts provide
fixed-point arithmetic is often an integral part of the algorithm a means of interfacing fixed-point components with other
design and analysis flow. Hardware Design Parts, available in the SystemVue blocks. Hardware Design Parts can also be configured
HDK, can be used to build, simulate and analyze fixed-point sys- to automatically collect information on dynamic range, overflows
tems. A library of over 45 functions, from low-level logic elements and underflows. The parts can be shown in the Fixed-Point
to more advanced signal-processing parts such as filters and fast Analysis Table to help engineers with system optimization.
Fourier transforms (FFTs), is available.
The SystemVue HDK supports use of standard-compliant IEEE
1666 SystemC fixed-point data types.
Figure 3. A cycle-accurate LMS transpose adaptive filter design using fixed-point generic primitive models
05 Keysight W1717 SystemVue Hardware Design Kit Data Sheet
Synthesizable HDL code generation Simulation
SystemVue's HDL Code Generation capability provides users an VHDL/Verilog co-simulation
easy path from schematic design to hardware. A user-created
With the SystemVue HDL co-simulation feature, users can
SystemVue sub-network model, with only synthesizable fixed-
simulate components represented in a HDL, VHDL and Verilog,
point parts from the HDK, can be used to generate VHDL/Verilog
in the same schematic with other SystemVue components. This
for the sub-network. For Xilinx's Virtex-4/5/6 FPGAs, SystemVue
integrated capability provides complete design flexibility and
provides a path to configure the clock and reset the user's HDL
complements other SystemVue features, including HDL genera-
design, as well as set up an ISE project or generate bit files
tion.
directly. For Altera's Cyclone IV/Stratix IV/Stratix V FPGAs,
SystemVue provides a similar path to set up a Quartus II project or
HDL co-simulation also allows the user's existing HDL code to be
generate programming files directly.
included in system-level simulations, and integrated with local
synthesizable fixed-point primitives. The HDL Code Generator
connects the user's HDL code with other Hardware Design Parts
to generate HDL codes for the whole design. It then runs the
Xilinx/Altera automatic implementation flow to generate the
programming file.
The ability to design all portions of a communications product
in one integrated environment eliminates design errors resulting
from disconnects among different design teams. By co-simulating
with HDL designs, users can easily incorporate existing HDL
intellectual property (IP) into new designs, or even co-simulate
with SystemVue-generated HDL. SystemVue integrates well
with the Mentor ModelSim or Aldec Riviera-PRO HDL simulators
via two simulation modes, either direct simulation from the
SystemVue user interface or hierarchical HDL project generation,
for full interaction and debugging using the external development
environments.
Hardware co-simulation
The SystemVue Hardware-in-Loop (HIL) co-simulation engine
allows the dynamic use of FPGA hardware to accelerate
computational tasks in a multi-threaded software environment.
Effectively, it circumvents traditional bottlenecks where the
accelerator hardware would only be usable by a single thread at a
time. The engine provides both the hardware implementation and
dynamic partial reconfiguration on Virtex-6 to implement func-
tions or measurements in FPGA hardware.
Hardware co-simulation requires a great deal of data stream
exchange between processors and FPGA cards. It can be
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