Service Manuals, User Guides, Schematic Diagrams or docs for : Agilent 5992-0108EN U4154B 4 Gb s State Mode Logic Analyzer Module - Data Sheet c20140908 [17]

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Keysight U4154B
4 Gb/s State Mode Logic Analyzer Module




                                          Data Sheet
Introduction

     Product Description
     The Keysight Technologies, Inc. U4154B logic analyzer system combines reliable data capture with powerful analysis
     and validation tools to enable you to quickly and confidently validate and debug high speed digital designs operating
     at speeds up to 4 Gb/s.


     Figure 1A shows the small Read          Figure 1B shows the trigger setup        Figure 1C and Figure 1D show the
     DQ eyes associated with a DDR4          to capture a burst of 8 Writes. The      state listing and waveform for this
     system operating at 2400 Mb/s data      trigger sequencer operates up to 2.5     capture.
     rate. This screen shot is captured      GHz, enabling accurate and precise
     in signal trace mode with no back       triggering.                              12.5 GHz Timing Zoom with 256 K
     to back bursts so that the eyes for                                              sample memory gives you
     the entire burst of 8 are displayed.                                             simultaneous state and
     The U4154B logic analyzer uses its                                               high-resolution timing
     unique eye scan capability to auto-                                              measurements covering a time
     matically place the sampling point                                               span of 20 us, which corresponds to
     in both time and voltage within the                                              43680 clock cycles at a 2133 MHz
     eye on each individual channel for                                               clock rate.
     optimal sampling reliability.




                                                                                      Figure 1B




     Figure 1A




     Figure 1C




                                             Figure 1D
03 | Keysight | U4154B 4 Gb/s State Mode Logic Analyzer Module - Data Sheet


Available memory depth up to 200 M
samples allows you to debug very complex
problems where the cause and symptoms
may be separated by several seconds. The
amount of memory can be upgraded after
purchase; see "Upgrades" in "Ordering
Information."

No need to sacrifice sampling resolution to
view more system activity. In timing mode,
if your system has bursts of activity
followed by times with little activity, you
can use transitional timing along with the
logic analyzer's deep memory to capture
seconds to minutes of activity at 400 ps
(2.5 GHz) sampling resolution. You also
have the flexibility to increase the amount
of time captured by excluding certain                    Figure 2. Timing Zoom precisely measures the time between the rising edge of the clock and the
buses or signals from the transition                     rising edge of DQS in a DDR system.
detector, for example clock or strobe
signals that add little useful information
to the measurement. In State mode, use                   For DDR2/3/4 and LPDDR/2/3/4 memory solutions under 2.5 Gb/s data rates, dual
store qualification to save only states of               sample mode is used to separate read and write data traffic. The B4621 DDR2/3/4
interest into memory.                                    decoder or the B4623B LPDDR/2/3/4 decoder reassembles the data to align with the
                                                         associated commands. (There's no need for the B4602A tool for DDR and LPDDR
The dual-sample mode has two benefits:                   solutions.)
For DDR memory signals up to 2.5 Gb/s,
it allows seperation of reads from writes,               For DDR4 and LPDDR4 memory solutions over 2.5Gb/s, double probing is required to
with automatic setup of the correct                      capture Read and Write DQ signals and dual sample mode is used to capture rising and
sampling positions for each. Dual sample                 falling edge DQ samples. Using this technique, a maximum of 34 DDR4 or LPDDR4 DQ
mode also allows acquisition of state                    signals operating over 2.5 Gb/s can be captured per U4154B module. Address,
(synchronous) data at rates up to 4 Gb/s.                command, and control signals for DDR or LPDDR memory do not require double probing
When used in this mode, the data will                    above or below 2.5Gb/s data rates.
appear in two labels. One label for rising
edge and another for falling edge cap-                   Support for bursty clock allows you to take measurements that include periods of
tures. The logic analyzer will be clocked                inactivity on the clock, such as power management transitions when the clock is inactive.
with one edge of the system clock. Labels
can be merged using the Keysight B4602A                  In state mode, the U4154B allows one clock input into pod 1 of the clocking module.
Signal Extractor tool. When operated in                    

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