Service Manuals, User Guides, Schematic Diagrams or docs for : Agilent HP 8663A Service Vol 3
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HP 8663A
SYNTHESIZED SIGNAL GENERATOR
(Including Options 001, 002, & 003)
Service Manual
SERIAL NUMi3ERS
This manual applies directly to irxtrumenti with
m-ial numbers prehed:
2234A to 2927A and all MAJOR changesthat apply to your instrument,
m~.Ol JUL91
For additional im~rtant information about trial
numbers, refer to TNS'THJMIENTS COVERED BY
THE MANUAL* in Section I.<
!l'hird Edition
This material may be reproducedby or for the U.S.
Government pur6uant to the Copyright License u.n-
dei-the clauseat DFB 52,227.7013(APR 1988).
Copyright@HEWLETT-PACKARD COMPANY 1982
EAST 24001 MISSION AVENUE, TAF C-34, SPOKANE, WASHINGTON, U.S.A. 99220
HEWLETT
Eta PACKARD
COPYRIGHT AND DISCLAIMER NOTICE
Copyright - Agilent Technologies, Inc. Reproduced with the permission of Agilent
Technologies Inc. Agilent Technologies, Inc. makes no warranty of any kind with regard
to this material including, but not limited to, the implied warranties of merchantability
and fitness for a particular purpose. Agilent Technologies, Inc. is not liable for errors
contained herein or for incidental or consequential damages in connection with the
furnishing, performance, or use of this material or data.
Model 8663A Volume 3 Conbmts
VOLUME 3 CONTENTS
Schematic ~hfmny/Trouble- PMtS
swvice Mock Assembly or Section ShootlnQ List
Sheet Diagram Page Page
Number Number Number
SSi3 SD3 A5A4 Fractional N Loop Referemx Divider s-401 6-109
SF.14 SD4 A5A3 Fractional N Loop Phase Detector 8-407 6-103
SW5 BD4 A5A5 Fractional N Loop VCO 0-417 6-111
SSl6 BW A5A2 Fractional N Loop N Divider 6-425 6-101
s.517 BD4 A5Al Fractional N Loop Accumulator 6-433 6-99
SSl8 SD6 A3A3 N Loop Dlvlder/Phase Detector 8-445 62.9
SSlQ BD5 A3A3 N Loop Divider/Phase Detector 8-455 649
SC.20 ED5 A3A4 N Loop VCO 8-?61 6-45
ss21 SD6 A3A5 Sum Loop Mixer 8467 6-49
ss22 SD5 A3A6 Sum Loop Phase Detector and Pr&me 6-473 6-51
SS23 BD5 A3A7 Sum Loop VGO 8479 6-55
SS24 BD5 A3A9 FM Sum Loop Mixer 8-485 6-63
SS25 SD5 A3AlO FM Sum Loop Phase Detector 8-491 6-65
SS28 BD6 A3A6 FM Sum Loop VCO E-495 6-59
ss21 ED6 A4A3 Distributor s-501 6-79
SS26 ED6 A4A3 Distributor E-505 6-79
ss29 ED6 Al2A.5 Low Pi-equency Down Converter E-509 6-223
ss30 ED6 AtZA3 Low Frequency Amplifier E-515 6-215
ss31 BD6 At2A2 UHF Modulator E-521 6-211
ss32 ED6 Al2A4 Doubler #l 8-525 6-219
S.93 ED6 A4A2 Doubler #Z 0-533 6-75
ss34 BD6 Al2Al RF Multiplexer and Power Amplifier 6-537 6-205
AT1 Output Attenuator
AT2 Output Attanuator
ss35 SD6 Ai2Ai RF Multiplexer and Power Amplifier 8-541 6-205
SS36 BD6 A4Al Automatic Level Control (ALC) 6-548 6-69
SW7 BD6 A4Al Automatic Level Control (ALC) 8-549 6-69
Model 0663A Service
SERVICE SHEET 13
A5A4 FRACTIONAL-N LOOP
REFERENCEBLOCK DIAGRAM 4
Table 4-l. Recommended Performance Tests
After Adjustments or Repaks
Table 5-2.. Post-Repair Adjustment Procedures
PRINCIPLES OF OPERATION
General
The Reference Divider divides the 10 MHz reference signal down to 100
kHz which is used as the reference signal to the phaxe detector.
This assembly also generates the sample pulse signal that clocks the
sample-hold circuit at the propep time.
Shaper
The shaper network consists of a diode'clamping network and a
differential amplifier. It provides the analog-to-TTL conversion.
Reference Divider
Ul and U4 form the divide-by-100 circuit which divides the 10 MHz
input signal to ppoduce the 100 kHz phase detector reference signal.
Sample Pulse Generator
The function of the sample pulse generator is to produce a 500 ns
pulse that is delayed by 1 microsecond from the leading ed,ge of the
phase detector reference signal. This is accomplished by detecting a
state in the divide-by-100 circuit which corresponds to the desired
delay time.
8-401/402
--
Figure 8.513, Al2A2 UHF Modulator Block Diagrams
Service Model 8663A
1 10
Figure 8-402 A5A4Fractimal-N Loop Reference Diuider Component Locator
8-404
PI0 A5A6
FRACTIONAL-N LOOI
L-- -- -- --
sLQt4L PREF,X 2*3`%A
N
!
,
/O A5A6 ---
I
lr
13
SERVICE SHEET
A5A4
Figure 8-403. A&M l+actiona~-N hop Refmnce
Divider Schematic
S-405/406
Model 8663A Service
SERVICE SHEET 14
A5A3 FRACTIONAL-N LOOP PHASE DETECTOR
REFERENCEBLOCK DIAGRAM 4
Table 4-l. Recommended I'erfoymance Tests
After Adjustments or Repairs
Table 5-2. Post-Repair Adjustment Procedures
PRINCIPLES OF OPERATION
General
The purpose of the Fractional-N Loop Phase Detector (A5A3) is to
dwelwp the FN Loop Error Voltage which is used to tune the VCO.
This FN Loop Error Voltage (tuning voltage) is developed by
integrating currents from the Phase Detector circuit, the
Fractional-N Correction Pulse ?Jidth to Current Converters, and the
Bias Sink circuit. These currents are integrated together by the
Current Summing Amplifier to develop a voltage. The Sample and Hold
circuit samples the voltage output from the Current Summing Amplifier
once each reference period and at the same time during each reference
period. The sampled voltage becomes the FN Loop Error Voltage.
When the Fractional-N Loop (FN Loop) is phase-locked, the tune
voltage must be a constant dc value, This means the voltage output
from the Current Summing Amplifier must be the same at every sample
period. In order to meet this condition the total of the currents
being integrated must be the same each reference period. To look at
it another way, the currents entering the summing node must equal the
currents leaving the summing node in order for the tune voltage to
remain constant. This concept, that when the FN Loop is
phase-locked, the currents entering the summing node equal. the
currents leaving the node is true for aI1 conditiwns, that is, for
the condition when the loop runs without a fractional part and for
the condition when it has a fractional part. The difference is that
when the loop operates with no fractional part the output from the
Phase Detector ci,rcuit remains constant. However, when the loop
operates with a fractional part, the output from the Phase Detector
circuit no longer remains constant but varies from reference period
to reference period. To compensate for the changing phase detector
output the outputs from the Fractional-N Correction Pulse Width to
Current Converters must also change. For example, if the Phase
Detector circuit supplies less current to the summing node, the
Fractional-N Correction Pulse Width to Current Converters must supply
more current so that the current entering the summing node is always
a constant value.
Phase Detector
The Phase Detector consists of a pair of flip-flops, U5A and B, and
gates U4D and U~C. The purpose of the Phase Detector is to generate
a pulse width proportional to the phase difference betw@en its two
input signals, the FN Loop IF (VCO/N) and the FN Loop PM Det
8.407
A3AI0 FM SUM LOOP PHASE DETECTOR (08662-60145)
20 MHz
BANDPASS
AMPLIFIER ATTENUATOR
3dB
L7
680n AMPLIFIER
NOTCH
'FILTERS'
+5V
L8
4 .7N
FM SUM LOOP
MIXER IF W26
24 0 w
Q2
R22
I0
I CIS
r 0 .047M
R23 CI6
P/0 A3AII 4220 O .OIu
LF LOOPS SECTION I -10V
FM SUM LOOP +5V
MOTHERBOARD -IOV
PHASE DETECTOR FM/CW SELECTOR
REFERENCE(CW) (08663-6Q3151 RII
FROM REFERENCE SECTION C4 100
LF MULTIPLIER J3 20MHz CW XA3A70
W32 1 (0 .5VPp) O .OIu 6
9 U4B
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