Service Manuals, User Guides, Schematic Diagrams or docs for : Akai LTA LTA-26C902 & LTA-32C902 & LTA-37C902 LTA-26C902 & LTA-32C902 & LTA-37C902

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LTA-26C902 & LTA-32C902 & LTA-37C902


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    Models:
LTA-26C902
LTA-32C902
LTA-37C902




   www.akai.ru
2
    Energy Saving Mode if there is no signal input.
 Multi Language On-Screen Display menu
     Ordinary and graphical user interface makes the menu operation more user-friendly
 Power Energy Saving Mode (power management mode)
    In PC mode, the LCD TV will automatically power off within 30 seconds and enter into the Power
 Energy Saving Mode if there is no VGA signal input. It will automatically exit from the Power Energy
 Saving Mode and work again when it received a valid VGA signal or press any button on the
 panel/remote control.
 Plug and Play
     It is no need to equip any installation software when the product is used as computer terminal display
 equipment
 Legerity, convenience, low power consumption
 Digital Photo Album Function(Only for CHD-W260F8P/CHD-W270F8P/ CHD-W320F8P/
CHD-W370F8P)
 Built-in DVD ModuleOnly for CHD-TD260F8 /CHD-TD270F8/CHD-TD320F8/CHD-TD370F8
Entirely Compatible to DVDSVCDVCDCDMP3
Compatible to PAL/NTSC Discs
High quality digital audio coaxial input enable you to feel as if sit in the theatre with the perfect classical
 hi-fidelity experience
Automatically delete unsuitable parts according to the chosen play levels (max.8 )(only for DVD discs
with play level control)
As many as 32 subtitles
As many as 8 audios


Unit IC Compositions
    LS08 chassis LCD TV is mainly composed of regulator IC IC
                                                          RF   video processor IC  Power Amplify
ICAnalog Video ICSystem Control IC and Key Control IC, see this IC frame as below:




                                                                                                             4
PCB Assembly
      It is mainly composed of TV BoardRemote Control Receiver(Signal Receiver) Side AV Board
K Board and Main Board. Hereunder function introduction to every PCB Assembly



Numbe        Parts                                          Description
  r
1        Main   Board   It is the core of signal processing for LCD TV, which takes responsibility of
         Assembly          transforming outer signal into the uniform digital signal identified by LCD display
                           with use of System Control IC.      TV and AV signals input from TV Board are
                           decoded by UOCIII to transport RGB signal which is to be transformed by
                           TDA8759 modulus to transport 24bit RGB digital signal, then it is to be
                           transformed by GM1601/GM1501 to produce LVDS signal displayed on the
                           screen, in addition, signals input from VGADVI would directly enter into
                           GM1501 procedure format transformation and on screen display.



                                                                                                       5
2   TV     Board      It is mainly composed of two tuners (main and sub tuners) AV/S HD signal
    Assembly          terminals and some peripheral processing IC. The main tuner demodulates RF
                      signal to IF signal, and the sub tuner produces CVBS signal, all signals are sent to
                      the main board after transfer.
3   Remote           t is composed of one indicator light and one remote control receiver, which enable
    Control            Users operate the TV conveniently and know its current working status simply with
    Receiver           a remote control..
    Assembly
4   Built-in Power    It can transform AC 220V into DC for ICs, including +24V+12V+5V and +5VS
    Board             power supply in standby mode.
    Assembly
5   K      Board      It consists of 7 function buttons by which users can operate the TV freely.
    Assembly


6   Screen            Screens for LS08 have the built-in adverse transformer which change DC into high
    Assembly            voltage AC signal to lighten the back light; The LCD screen is used to display the
                        image after the image signal has been processed by the main board.
                      ,
7   Side AV Board     It is used for earphone output, AV input, S input




                                                                                                    6
           CHAPTER TWO                     MAIN ICs FUNCTION INTRODUCTION

GENERAL INTRODUCTION:
                                                       TV Board
Number           Location                Type                                  Main Function
1           UT1               TMI4-C22P2RW                  Audio and image intermediate frequency signal
                                                            output
2           UT2               TAD5-C2IP1RW                  Sub picture CVBS signal output
                                                  Main Board
3           U302U303          24LC21A T/SN                  EEPROM
4           U701              24LC32A T/SN                  Buffer
5           U306,U307,UA3     FSAV330QSCX                   Switch selection
6           K201              K7262N                        Audio surface filter
7           K202              K9352N                        Audio surface filter
8           U6                TPA3002D2PHPR                 Audio amplifier
9           U801              AM29LV800DT-70EC              Flashcontrol program inside
10          U700              GM1501-BD                     Video processor
11          U201              TDA15063H-N1B06557            AV decoder
12          U402              SAA7115HL/V1                  Sub channel video decoder
13          U305              SM5302AS-G-ET                 High definition signal filter
14          U400              TDA8759HV/8/C1                Video signal modulus transformer
15          U5                TDA9178T/N1                   Video signal picture amendment
16          U600              MT46V2M32LG-4                 Frame buffer


.ICs FUNCTION INTRODUCTION IN DETAILS

Main Tuner (TMI4-C22P2RW)
             Pin                         Definition                                 Description
1                              AGC                                Auto gain control
2                              UT                                 NC
3                              ADD                                Ground
4                              SCL                                IIC bus (Clock)
5                              SDA                                IIC bus   (Data)
6                              NC                                 NC
7                              +5V                                Power supply
8                              NC                                 NC
9                              30V                                To produce 0~30V tune voltage
10                             NC                                 NC
11                             IF                                 Intermediate frequency TV signal
                                                                  Intermediate frequency TV signal


Sub Tuner    (TAD5-C2IP1RW):
     Pin                    Definition                                        Description
1                  AGC                                Auto gain control
2                  NC                                 NC
                                                                                                        7
3               ADD                              Ground
4               SCL                              IIC bus (Clock)
5               SDA                              IIC bus (Data)
6               NC                               NC
7               +5V                              Power supply
8               NC                               NC
9               33V                              To produce 0~30V tune voltage
10              NC                               NC
11              IF                               Intermediate frequency output (NC)
12              IF                               Intermediate frequency output (NC)
13              SW0                              Band control
14              SW1                              Band control
15              NC                               NC
16              SIF                              NC
17              AGC                              Auto gain control
18              VEDIO                            CVBS signal output
19              +5V                              Power supply
20              AUDIO                            NC



GM1501
   GM1501is a kind of processing chassis for dual channels image and video, which is mainly used for
LCD displays and integrative TV products. With the resolution of WUXGA, it not only supports PIP
technique, but possesses some IC functions applied to image catch process and clock display. It
integrates high velocity AD converter, PLL, high reliability DVI receiver, X86 series miccontrol and LCDS
inverter. See the features as below:

Main Features
 High quality image zoom function;
 Analog RGB signal input interface;
 Intelligent output signal auto identification;
 Integrated high-power PLL output;
 High-reliable self-adaptive DVI input interface;
4:4:4/4:2:2/CCR656/601 8/16/24bit digital video interface;
 Embedded IC for adjustments of gaincontrastbrightnesscolor saturationhue and fleshtone;
 Efficiency in reducing EMI electromagnetism inference;
 Inclined grain processing with small angle;
 High quality video processing;
 Programmable output format;
 Embedded LVDS transport;
 Advanced OSD;
 Embedded micro controller
Pin   Description :

                     Pin                Name                           Description
                                          Analog Signal Input Port

                                                                                                        8
L3                   AVSYNC               ADC vertical synchronization signal input
L4                   AHSYNC               ADC horizontal synchronization signal input
N2                   VGA-SCL              VGA lock input
N1                   VGA-SDA              VGA digital input
D1D2                 RED+RED-             Red analog signal input
C3                   SOG                  Green synchronization signal
C1C2                 GREEN+-              Green analog signal input
B1B2                 BLUE+BLUE-           Blue analog signal input
A2,B3,E3,D3          ADC3.3               ADC3.3Vpower supply
A3A4                 ADC1.8               ADC1.8Vpower supply
A5B4                 ADC-DGND             ADC digital ground
C4D4E1E2E4           ADC-AGND             ADC analog ground
                               DVI Input Output Port
N4                   DVI-SCL              DDC interface , serial clock signal
N3                   DVI-SDA              DDC interface serial data signal
A6B6                 RXC+RXC-             DVI clock input signal
A8A10                RX0+RX2+             DVI input port
B8B10                RX0-RX2-
B11                  REXT                 Exterior exit resistance
C6C11                DVI-3.3              DVI 3.3V power supply
D6D8D10              DVI-1.8              DVI 1.8V power supply
A7,A11,B5,B7,C7,D7   DVI-GND              DVI ground
D11
                            Low Bandwidth ADC Port
C13                  LBADC-33             ADC3.3Vpower supply
A12B12C12            LBADC_IN1            ADC analog input channel
                     LBADC_IN3
D12                  LBADC_RETURN         Channel analog ground
D13                  LBADC-GND            Power supply voltage analog ground
                                   OCM IC Port
AA1~AA3,Y1~Y3,       OCMADDR0             Address input output port
W1~W3,V1~V4,         OCMADDR19
U1~U4,T1~T3
AB1~AB3,AC1~AC3,     OCMDATA0~            Data input output port
AD1~AD4,AE1~AE3,     OCMDATA15
AF1~AF3
                            OCM Port Control Signal
R1T4P1P2             ROM_CSn~             Part selection signal
                     ROM_CS2n
R2                   OCM_REn              Read enable signal
R3                   OCM_WEn              Write enable signal
L1                   OCM_INT2             Interrupt
L2                   OCM_INT1
M1                   OCM_UDO              OCM data output
M2                   OCM_UDI              OCM data input
D25                  OCM_TIMER1           OCM timer input
                                                                                        9
                      Standard Definition Video Control Port
D16                SVCLK                   SV pels clock input
C14                SVHSYNC                 SV horizontal synchronization signal input
B14                SVVSYNC                 SV vertical synchronization signal input
A14                SVODD                   Scan status input
A17                SVDV                    SV data input
                         Standard Definition Video Data Port
D14,D15,A15,A16,   SVDATA7~                SV ITU656 data input
B15,B16,C15,C16    SVDATA0
                                 Video Control Port
A20                VCLK                    Video pels clock signal
D19                VHS_CSYNC               Video horizontal synchronization signal input
C20                VVS                     Video vertical synchronization signal input
B20                VODD                    Scan status input
D20                VDV (VSOG)              Video data input
B17                VCLAMP                  Video clamp enable output
A21,A22,A23,B21,   VGRN7~ VGRN0            Green signal or Y signal input
B22,C21,C22,D21
C17,C18,C19,A18    VRED7~ VRED0            Red signal or V/Cr/Pr signal input
A19,B18,B19,D18
B23,B24,B25,A24    VBLU7~ VBLU0            Blue signal or U/Cb/Pb signal input
A25,C23,C24,D24
                                Screen Control Port
A26                PPWR                    Screen power control
B26                PBIAS                   Screen bias control
D26C25C26          PWM2 ~PWM0              Pulse width modulation output
AC7                DCLK                    Pels clock output
AC16               OEXTR                   Connect external LVDS bias resistance
                                     LVDS Port
AE14~AE16,AE19~    A0-~A3-, A0+~A3+        Low voltage difference data input
AE23,AF13~AF16     B0-~B3-, B0+~B3+
AF19~AF23,AF11
AD14,AD11,AE13     LVDS_SHIELD[5] ~        Low voltage difference protect output
AE11,AC11,AF10     LVDS_SHIELD[0]
AE12,AF12,         AC+,AC-,BC+,BC-         Low voltage difference protect input
AF20,AE20
                             Screen Port Power Supply
AD12,AD13,AC12     LVDSB_3.3               LVDS B channel power supply
AC13,AC14,AC15     LVDSB_GND               B channel ground
AC20,AC21,AC22     LVDSA_3.3               LVDS A channel power supply
AD19,AC19,AC20     LVDSA_GND               A channel ground
AE17               VDDD33_LVDS             Analog power supply
AD17               VSSD33_LVDS             Analog ground
                         Clock Composite and Power Supply
G4                 XTAL                    crystal oscillator interface

                                                                                           10
          F2               VDDD33_PLL            Digital power supply
          H1               VDDD33_SDDS
          J1               VDDD33_DDDS
          G2               VSSD33_PLL            Digital ground
          J4               VSSD33_SDDS
          K4               VSSD33_DDDS
          F4               VDDA33_RPLL           Analog power supply
          G1               VDDA33_FPLL
          H3               VDDA33_SDDS
          J3               VDDA33_DDDS
          F3               VSSA33_RPLL           Analog ground
          H4               VSSA33_FPLL
          H2               VSSA33_DDDS
          J2               VSSA33_DDDS
          G3               TCLK                  Reference clock signal input
          K2               ACS_RSET_HD           External resistance port
                                         System Signal
          K1               RESETn                Reset signal
          M3M4             IR0IR1
          P4               MSTR_SCL              Main clock output signal
          P3               MSTR_SDA              Main data output/input signal 
          R4               EXTCLK                External clock input
Frame Storage Interface
U24,U23               FSCLKp,FSCLKn       Fine storage clock output
V24,V25               FSRAS,FSCAS         Address output
V26                   FSWE                Write enable port
W26                   FSCKE               Read enable port
J24                   FSVREF              Reference voltage input
K26                   FSVREFVSS           Reference voltage ground
W25                   FSVREF              Reference voltage input
W24                   FSVREFVSS           Reference voltage ground
L26                   FSDQS               Data filter
F24~F26,G23~G26       FSDATA31~           Data input output port
H24~H26,J25,J26,      FSDATA0
R24~R26,P24~P26
N23~N26,.......
T24,T25,U25,U26       FSDQM3~ FSDQM0      Data output mark
Y26                   FSBKSEL1            Layer address
Y25                   FSBKSEL0
AA24~AA26             FSADDR11~           Range address output
AB24~AB26,            FSADDR0
AC24~AC26
AD24~AD26
E23, F23, H23, J23,   FS_2.5              2.5V power supply
L23,M23,P23, R23,
T23,V23,W23,Y23,
                                                                                  11
AA23,AB23,AC23
K23                     VDDA18_DLL              1.8V power supply
K25                     VSSA18_DLL              Power supply ground
Digit power supply
K10,K11,K16,K17,        CORE_1.8                1.8V power supply
L11,L16,T11,T16,
T17,U10,U11,U16,U17
D23, W4,Y4, AA4,        IO_3.3                  3.3V power supply
AB4,AC4,AC6,D17,
D22,AC8,AC10
K12,K13,K14,K15,        D_GND                   Power ground
L10,L12,L13,L14,
L15,L17,M10,M11,
M12,M13  
A1ACD5AC17 NO_CONNECT                           NC
K3F1


GM1501Internal Diagram




TDA8759
   TDA8759 is a triple 8-bit video converter interface. The IC converts a RGB analog signal into a 24bit
RGB or YUV or YCbCr digital signal , or converts a YUV or YCbCr analog signal into a YUV or RGB digital
signal with a sampling rate up to 81 Msps. The IC supports resolutions from 480i and VGA to HDTV and
XGA.

                                                                                                      12
    Main Features:
     Triple 8-bit Analog-to-Digital Converter (ADC)
    Three independent analog video sources up to 81 Msps selectable by I2C-bus
    Auto check on interval scan video signal
    1.8Vand 3.3Vsupplies
     Low gain variation with temperature
    Output format RGB 4:4:4, YUV 4:4:4, YUV 4:2:2 ,CCIR 656 or YUV 4:2:2 semi-planar standard on
output bus
    I



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