Service Manuals, User Guides, Schematic Diagrams or docs for : COMPAQ Note book evo 610c Fenway2.0-SI
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Engineer
Engr_Name
Drawn by
Kevin Tseng
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Fenway2.0
TABLE OF CONTENTS
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 1 of 51
EE1 Friday, April 19, 2002 9:58:54 am 110 SI
ITP Northwood CK TITAN
(Micro-FCPGA)
mPGA478
AGP/M7-P
Display Cache
DDR_SODIMM0
DDR_SODIMM1
Brookdale-M
Multibay HDD
CONTROLLER LAN Interface
LOM
Bluetooth
CONN A
CONN B
USB0
USB1
Dock
USB3
USB2
USB4
Dock
ICH3-M
USB
PCI 1420
AC'97 CODEC CARDBUS Mini PCI
System
DC/DC FWH
Module
BATTERY
Docking SMC/KBC
Engineer
Engr_Name
Drawn by
Kevin Tseng
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Fenway2.0
BLOCK DIAGRAM
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 2 of 51
EE1 Wednesday, January 23, 2002 10:02:33 pm 110 SI
CN506 +VADPTR
+VADPTR
ADPT
+VCC_CORE
+VBAT
+VCC_CORE
+VBAT SWICHING
MOSFET
ISL6215
ISL6205
+VADPTR_SW
+VADPTR_SW +V2.5
I/O BOARD
+V1.5S
+V1.8ALWAYS +V1.8S
3V ON
+V3 +VCC_VID
5V ON
CN512 CN516
+V1.5S
+VBAT 1.5V +V1.25
+V3S
2.5VA +V2.5A
CN513 +V3ALWAYS
3V +V5
5V +V5a
+VADPTR_SW
12V +V12
+V5S
5VALWAYS +V5ALWAYS
CN512
DC/DC BOARD
+V12
+V5ALWAYS
Engineer
Engr_Name
Drawn by
Kevin Tseng
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Fenway2.0
BLOCK DIAGRAM
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 3 of 51
EE1 Wednesday, January 23, 2002 10:03:29 pm 110 SI
L513 +V3S
NFM40P12C223
(15/5) 1 2
2
1 3 4 C569
C568 10NF_16V
C583 C567 C582 C581 1 C570
4 3
1 1 1 1 1
2 2 2 2 2
0.01UF 0.01UF 0.01UF 0.01UF 8 7 6 5
22UF_6.3V 0.01UF
(10/5) (10/5)
1 L15 2
BLM11A221S
U11 1 C152
2 0.01UF
1 C151
22UF_6.3V
1 VDD VDDA 26
8 VDD
14 VDD VSSA 27 1 2
19 VDD R603 49.9_1%
32 CLK_CPU_BCLK_3 33_1% R169
+V3S Place crystal within 500 VDD CPU2 45 1 2 5-
CLK_CPU_BCLK
37 VDD CLK_CPU_BCLK#_3 33_1% R168
mils of CLK_TITAN
C154 OPEN
46 VDD CPU2# 44 1 2 5-
CLK_CPU_BCLK#
TP84
1 50 VDD
1 2
1 2
R604 49.9_1% R601 49.9_1%
X2 CLK_MCH_BCLK_3 33_1% R171 1 2
1 1
2 XTAL_IN CPU1 49 1 2 9-
CLK_MCH_BCLK
R600 R573 C153 OPEN 14.318MHZ CLK_MCH_BCLK#_3 33_1% R170
3 XTAL_OUT CPU1# 48 1 2 9-
CLK_MCH_BCLK#
OPEN 1K 1 2
2 1 2
R177 49.9_1% R602 49.9_1%
2 2 R577 CLK_ITP_3 CLK_ITP_CPU_3
1 2 TP2 40 SEL2 CPU0 52 TP69 33_1% 1 R175 2 1 R435 2 5- 1 2
CLK_ITP_CPU R433
1K OPEN 1 244-,6-
CLK_ITP
CPU0# 51 TP16 CLK_ITP#_3 33_1% 1 R771 2 CLK_ITP_CPU#_3 1 2 5- 0
R599 CLK_ITP_CPU#
H_BSEL1 5- TP19 1 2 TP6 55 SEL1 R598 OPEN R770
OPEN 66INPUT 24 49.9_1%
1 2 1 R570 244-,6-
R571 CLK_AGPCONN_3 R553 CLK_ITP#
H_BSEL0 5- TP20 1 2 TP10 54 SEL0 66BUF2 23 33_1% TP18 44-,15-
CLK_AGPCONN 0
TP17 1 2
R578 OPEN R554 CLK_MCH66_3 R143
SLP_S1#_3R 20-,15- 1 2 1 2 25 PWRDWN# 66BUF1 22 33_1% TP22 8-
CLK_MCH66
TP15 1 2
0 1 1 33 CLK_ICHHUB_3 233_1%
PCISTOP#_3 20- 34 PCI_STOP# 66BUF0 21 R552 1 TP23 44-,19- CLK_ICHHUB
1 R579 2
49-,47-,41-,28-,26-,20- R572
SLP_S3#_3R R575 R188 CLK_ICHPCI_3
OPEN 1K CPUSTOP#_3
OPEN 48-,20- 1 2 53 CPU_STOP# PCIF2 7 TP14 R148 1 233_1% TP21 44-,19- CLK_ICHPCI_3R
2 2 0
28 VTT_PWRGD# PCIF1 6
1 R576 2
R574
+V3S 10K 1 2 43 MULT0 PCIF0 5
OPEN
29 CLK_CBPCI_3 R144
TP12 ICH_SMDAT_3 45-,21-,19-,11- SDATA PCI6 18 1 2 33_1% 44-,24- CLK_CBPCI_3R
TP4
TP5 ICH_SMCLK_3 30
45-,21-,19-,11- SCLOCK PCI5 17
TP3
TP1 33 DRCG0 PCI4 16 CLK_MINIPCI_3 1 R145 2 33_1% 44-,36- CLK_MINIPCI_3R
35 DRCG1_VCH PCI3 13
+V3S CLK_FWHPCI_3 R551
42 IREF PCI2 12 1 2 33_1% 44-,22- CLK_FWHPCI_3R
PCI1 11 CLK_MSICPCI_3 1 R146 2 33_1% 44-,21-
1 CLK_MSIOPCI_3R
1
41 VSSIREF
1 R142 R167 R147
475_1% 4 PCI0 10 CLK_USB_3 1 2 33_1% 50-
10K VSS CLK_USB_3R
R580 2 9 VSS R166
OPEN 15 USB 39 CLK_ICH48_3 1 2 33_1% 44-,20- CLK_ICH48_3R
2 VSS
2 20 VSS
Q514 3 31 VSS DOT 38
D 36 VSS
1
49-,48-,45-,20-
R581 2 2G 47 REF 56 CLK_MSIO14_3 1 R172 2 33_1% 44-,21-
VGATE_U VSS CLK_MSIO14_3R
0 S
1 NDS7002A 1 R173 2 33_1% 44-,20- CLK_ICH14_3R
1 C584
ICS_950805_TSSOP_56P
2
OPEN
Engr_Name
Kevin Tseng
INVENTEC
A3
Fenway2.0
CLK TITAN
4 51
110 SI
H_A#(16:3) 44-,9- CN509 H_D#(15:0) 44-,9-
N5 G1 44-,9- 44-,9-
A16# ADS# H_ADS# H_D#(47:32)
N4 A15# AP0#
AC1 CN509
N2 V5 D25 T23
A14# AP1# AA3 D15# D47# T22
M1 A13# BINIT# J21 D14# D46#
G2 T25
ADDR GROUP 0
N1 A12# BNR# 44-,9- H_BNR# D23 D13# D45#
M4 D2 44-,9- C26 T26
A11# BPRI# H_BPRI# D12# D44# R24
M3 A10# H21 D11# D43#
L2 G22 R25
A9# L25 D10# D42# P24
M6 A8# DP3# B25 D9# D41#
L3 K26 +VCC_CORE C24 R21
DATA GRP 2
DATA GRP 0
A7# DP2# D8# D40#
K1 K25 C23 N25
A6# DP1# J26 D7# D39# N26
L6 A5# DP0# B24 D6# D38#
K4 E2 44-,9- D22 M26
A4# DEFER# H2 H_DEFER# D5# D37# N23
K2 A3# DRDY# 44-,9- H_DRDY# C21 D4# D36#
44-,9- 9- L5 H5 44-,9- A25 M24
H_REQ#(4:0) H_ADSTB#0 ADSTB0# DBSY# H_DBSY# D3# D35#
H3 A23 P21
REQ4# R109 1 D2# D34# N22
J3 REQ3# 54.9_1% B22 D1# D33#
J4 U6 H_BR1# 1 2 R106 B21 M23
REQ2# TESTHI8 220 D0# D32#
K5 W4 H_BR1# 9- E21 P26 9-
REQ1# TESTHI9 Y3 H_DINV#0 DINV0# DINV2# R22 H_DINV#2
J1 REQ0# TESTHI10 H6 H_BR1# 2 H_DSTBN#0 9- E22 STBN0# STBN2# 9- H_DSTBN#2
9- 9- F21 P23 9-
BR0# H_BR0# H_DSTBP#0 STBP0# STBP2# H_DSTBP#2
R134 +VCC_CORE
CONTROL
AB1 AC3 H_IERR_PU# 1
10K 2 44-,9- 44-,9-
A35# IERR# H_D#(31:16) H_D#(63:48)
Y1 H25 AA24
A34# W5 D31# D63# AA22
W2 A33# INIT# 44-,19-,5- H_INIT# +VCC_CORE K23 D30# D62#
44-,9- V3 J24 AA25
H_A#(31:17) A32# G4 D29# D61#
U4 44-,9- L22 Y21
A31# LOCK# H_LOCK# D28# D60# Y24
T5 A30# M21 D27# D59#
ADDR GROUP 1
V6 1 Y23
W1 A29# MCERR# H24 D26# D58#
R6 R123 G26 W25
A28# 51.1_1% D25# D57#
DATA GRP 3
DATA GRP 1
V2 L21 Y26
A27# AB25 D24# D56# W26
T4 A26# RESET# 2 9-,6- H_CPURST# 44-,9- H_RS#(2:0) D26 D23# D55#
U3 F4 F26 V24
A25# RS2# G5 D22# D54# V22
P6 A24# RS1# E25 D21# D53#
U1 F1 F24 U21
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