Service Manuals, User Guides, Schematic Diagrams or docs for : Compal COMPAL_LA-1121
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A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BLOCK DIAGRAM
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
Model Name : 888M3
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PCB No : LA-1121
Revision : 1.0 Mobile Tualatin
4 4
or
Coppermine-T Thermal Sensor CK TITAN CPU VID & All
(uFCBGA/uFCPGA) MAX1617MEE ICS9250-38 reference voltage
PAGE 4,5,6 PAGE 5 PAGE12 PAGE 7
PSB
Almador-M
CRT & TV-Out AGP 4X GMCH-M SO-DIMM * 2
CONN. CONN. AGP Bus Interface Memory Bus PAGE 13,14
PAGE 16
BANK 2,3,4,5
625 BGA
3 PAGE 15 3
PAGE 8,9,10,11
IEEE 1394
Interface
HUB
USB & BlueTooth USB
TI TSB43AB22
PAGE 27 PAGE 22
SmartMedia with SD
TC6371AF
HDD Connector PAGE 29
ATA 66/100
PAGE 20
LAN FAN on controller &
RTL8100-L TEMP. sensing circuit
PAGE 21
CD-ROM Connector Audio CD-DJ PAGE 35
OZ163
ICH3-M
PAGE 20
Rev.C
2
PAGE 30 421 BGA Mini PCI 2
PCI BUS DC/DC Interface
Socket
PAGE 17,18,19 PAGE 28
RTC Battery
PAGE 37
LPC
CardBus
TI Slot 0/1
PCI1420 PAGE 24 BATTERY
PAGE 23
Super I/O Embedded Charger
PAGE 41
LPC47N227 Controller
PAGE 25 NS PC87591 AC'97
PAGE 33 CODEC
CS4299 POWER
PAGE 31
Interface
1 BIOS & I/O PAGE 40,42,43,44 1
PORT
PAGE 34
Parallel FIR FDD Scan KB Audio Jack Audio Amplifier
Title
Compal Electronics, inc.
PAGE 26 PAGE 26 PAGE 20 PAGE 15 PAGE 32 PAGE 32
SCHEMATIC, M/B LA-1121
Size Document Number Rev
Custom 1C
401191 (FOR ATL02 / ACL00)
Date: , 27, 2001 Sheet 2 of 87
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Voltage Rails
PIR
Power Plane Description S1 S3 S5 REV 0.2
Date Page Description
VIN Adapter power supply (19V) N/A N/A N/A
5/8 29 Modification toshiba SM+SD function
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
5/8 32 Modification audio volume control function
+VCC_H_CORE Core voltage for CPU ON OFF OFF
5/8 42 ADD system thermal protection
+VTT 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
5/14 33 DEL R244 ,Add D44
+1.5V 1.5V power rail ON ON OFF
REV 0.3
+1.5VS AGP 4X ON OFF OFF
Date Page Description
+1.8V 1.8V power rail ON ON OFF
5/23 5 U8 Vcc plane modifty to +5VALW
+1.8VS 1.8V switched power rail ON OFF OFF
5/23 18 DEL R90,R89,R281
+2.5V 2.5V power rail ON ON OFF
5/23 32 R448 change gnd to +5VCD, R479 change +5VCD to gnd.
+3VALW 3.3V always on power rail ON ON ON*
5/23 37 U2.4 link to U20.8
+3V 3.3V power rail ON ON OFF
5/23 30 Add R519.
+3VS 3.3V switched power rail ON OFF OFF
5/23 5 U9.AF19 add R517 link to +1.5VS
+5VALW 5V always on power rail ON ON ON*
5/23 25 Modifty LPC_RST# timing. Add U55,D45,R518.
+5V 5V power rail ON ON OFF
5/31 27 JP15.8 connector to U29.57
+5VS 5V switched power rail ON OFF OFF
5/31 25 ADD R520, Add net name BT_DET# to U29.57
+12VALW 12V always on power rail ON ON ON*
2 5/31 34 Modifty net name ANT_SW to WL_OFF#, ADD R221 2
+12VS 12V switched power rail ON OFF OFF
5/31 28 Modifty net name RFOFF# to WL_OFF#
RTCVCC RTC power ON ON ON
5/31 35 DEL R19
REV 0.4
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Date Page Description
7/3 16 Del L23,R14,R12,R10,R6,R8
7/3 27 ADD C720,C721,C722,C723,C724,C725
External PCI Devices 7/3 29 IDSEL0 change to PCI_AD26, INTA#/INTB# change to PIRQC#/PIRQD#
7/10 24 Add U58,U59,R531,R532,R533,R534,C718,C719
Device IDSEL# REQ#/GNT# Interrupts
AGP 4X CONN. PIRQA 7/17 29 Del SD function
IEEE 1394 AD16 0 PIRQA 7/18 29 Change IDSEL to PCI_AD22
CardBus AD20 2 PIRQA/PIRQB 7/23 21 DEL C15
REV 0.5
LAN AD17 3 PIRQB
Mini-PCI AD18 1/4 PIRQC/PIRQD
Date Page Description
8/13 15 Add R544 reserve for sus_stat# and stp_agp#
SD/SM AD22 PIRQC/PIRQD
8/13 29 Add R545 pull-up signal SM_LED to SMC_VCC,Add@ in
3 3
U62,C729,R486
8/13 35 Change R543 pull-up form SMC_VCC to +5VS
8/13 29 Add R546,R547 signal PCIRST#,CBRST#
EC SM Bus1 address EC SM Bus2 address 8/13 37 Del U2,Q4,R330
8/16 10 Add Signal TV_out_DDC2CCLK,TV_out_DDC2DATA
Device Address Device Address ,VCH_I2CCLK,VCH_I2CDATA,AGP_DDCCLK,AGP_DDCDATA
Smart Battery 0001 011X b MAX1617MEE 1001 110X b 8/16 10 Add R551.R552. DEL R225,R235
EEPROM(24C16/02) 1010 000X b OZ163 0011 0100 b 8/16 15 Add RP38,RP39
(24C04) 1011 000Xb Smart Battery 0001 011X b 8/16 16 Add R553,R554,R555
Docking 0011 011X b 8/17 34 Del R29, Add R557, R558
DOT Board XXXX XXXXb 8/17 20 Add R556
REV 1.0
Date Page Description
8/31 5 Q6 RESERVE
ICH3-M SM Bus address
REV 1.A
Device Address
Date Page Description
9/6 12 Add D47 and R562
4 4
Clock Generator ( ICS9238-50) 1101 0000
SDRAM Select ( 74HC4052 ) 1010 0000
CPU Voltage VID select ( F3565 ) 0110 111Xb
Title
Compal Electronics, inc.
SCHEMATIC, M/B LA-1121
Size Document Number Rev
Custom 1C
401191 (FOR ATL02 / ACL00)
Date: , 27, 2001 Sheet 3 of 87
A B C D E
A B C D E
+VCC_H_CORE
1 1
AC21
AC19
AC17
AC15
AC13
AC11
AB22
AA21
AB20
AA19
AB18
AA17
AB16
AA15
AB14
AA13
AB12
AA11
AB10
W21
AC9
AC7
M22
AA9
AB8
AA7
G21
D22
H22
N21
R21
U21
D20
D18
D16
D14
D12
D10
E21
K22
P22
V22
Y22
E19
E17
E15
E13
E11
F22
T22
F20
F18
F16
F14
F12
F10
L21
J21
G5
D8
D6
H6
N5
E9
E7
E5
K6
V6
F8
F6
T6
J5
H_A#[3..31] U9A H_D#[0..63]
8 H_A#[3..31] H_D#[0..63] 8
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
H_A#3 K1 A16 H_D#0
H_A#4 A#3 D#0 H_D#1
J1 A#4 D#1 B17
H_A#5 G2 A17 H_D#2
H_A#6 A#5 D#2 H_D#3
K3 A#6 D#3 D23
H_A#7 J2 B19 H_D#4
H_A#8 A#7 D#4 H_D#5
H3 A#8 D#5 C20
H_A#9 G1 VCC C16 H_D#6
H_A#10 A#9 D#6 H_D#7
A3 A#10 D#7 A20
H_A#11 J3 A22 H_D#8
H_A#12 A#11 D#8 H_D#9
H1 A#12 D#9 A19
H_A#13 D3 A23 H_D#10
H_A#14 A#13 D#10 H_D#11
F3 A#14 D#11 A24
H_A#15 G3 C18 H_D#12
H_A#16 A#15 D#12 H_D#13
C2 A#16 D#13 D24
H_A#17 B5 B24 H_D#14
H_A#18 A#17 D#14 H_D#15
B11 A#18 D#15 A18
H_A#19 C6 E23 H_D#16
H_A#20 A#19 D#16 H_D#17
B9 A#20 D#17 B21
H_A#21 B7 B23 H_D#18
H_A#22 A#21 D#18 H_D#19
C8 A#22 D#19 E26
H_A#23 A8 C24 H_D#20
2 H_A#24 A#23 D#20 H_D#21 2
A10 A#24 Address D#21 F24
H_A#25 B3 Lines D25 H_D#22
H_A#26 A#25 D#22 H_D#23
A13 A#26 D#23 E24
H_A#27 A9 B25 H_D#24
H_A#28 A#27 D#24 H_D#25
C3 A#28 D#25 G24
H_A#29 C12 H24 H_D#26
H_A#30 A#29 D#26 H_D#27
C10 A#30 D#27 F26
H_A#31 A6 L24 H_D#28
A#31 D#28 H_D#29
A15 H25
A14
B13
A12
A#32
A#33
A#34
Mobile Data
Signals
D#29
D#30
D#31
C26
K24
G26
H_D#30
H_D#31
H_D#32
8 H_REQ#[0..4]
H_REQ#[0..4]
H_REQ#0 R1
A#35
REQ#0
Tualatin D#32
D#33
D#34
D#35
K25
J24
K26
H_D#33
H_D#34
H_D#35
H_REQ#1 L3 F25 H_D#36
H_REQ#2 REQ#1 D#36 H_D#37
T1 REQ#2 Request D#37 N26
H_REQ#3 U1 Signals J26 H_D#38
H_REQ#4 REQ#3 D#38 H_D#39
L1 REQ#4 D#39 M24
T4 U26 H_D#40
RP# D#40 H_D#41
8 H_ADS# AA3 ADS# D#41 P25
L26 H_D#42
D#42 H_D#43
D#43 R24
W2 R26 H_D#44
AERR# D#44 H_D#45
AB3 AP#0 D#45 M25
P3 Error V25 H_D#46
+1.5VS AP#1 D#46 H_D#47
C14 BERR# Interface D#47 T24
R331 1.5K AF23 M26 H_D#48
BINIT# D#48 H_D#49
1 2 AF4 IERR# D#49 P24
3 H_D#50 3
D#50 AA26
R87 10 T26 H_D#51
D#51 H_D#52
1 2 A7 BREQ0# D#52 U24
C4 Arbitration Y25 H_D#53
NC D#53 H_D#54
C22 NC Signals D#54 W26
AD23 V26 H_D#55
NC D#55 H_D#56
8 H_BPRI# R2 BPRI# D#56 AB25
L2 T25 H_D#57
8 H_BNR# BNR# D#57
V3 Snoop VSS VCC Y24 H_D#58
8 H_LOCK# LOCK# D#58
Signals W24 H_D#59
D#59 H_D#60
D#60 Y26
AA2 AB24 H_D#61
8 H_HIT# HIT# D#61
U2 AA24 H_D#62
8 H_HITM# HITM# D#62
T3 V24 H_D#63
8 H_DEFER# DEFER# D#63
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
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