Service Manuals, User Guides, Schematic Diagrams or docs for : Compal COMPAL_LA-1911-REV_1.0Sec
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A B C D E
1 1
SAPPORO 150 (DAL00)
2 2
LA-1911 REV1.0 Schematic
3 Desktop Prescott/Northwood uFCPGA-478 CPU 3
Springdale(865PE)+ICH5+nVIDIA NV34M(64MB VRAM)
2003-08-06
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Compal Electronics, Inc.
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Title
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Cover Page
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Size Document Number Rev
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B 0.2
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Date: Friday, August 08, 2003 Sheet 1 of 57
A B C D E
A B C D E
DAL00 LA-1911 BLOCK DIAGRAM
4 4
Desktop Northwood
Desktop Prescott Thermal Sensor Clock Generator FANController
(uFCBGA/uFCPGA-478) ADM1032 ICS952623 CPU VID RTC Battery
PAGE 4,5,6 PAGE 5,16 PAGE15 PAGE 5 PAGE 40
FSB
CRT&LVDS 800MHz
ConnectorPAGE 22 DC/DC Interface
PAGE 43
2 6 6/333/400MHz
(2.55V)
AGP AGP 8X Intel Springdale SO-DIMM x 2(DDR)
TV-OUT
4 Pin-Connector NVIDIA-NV34M AGP Bus MCH 865PE M e m o r y Bus BANK 0,1,2,3 PAGE 12,13,14
3
PAGE 22
PAGE 16,17,18,19
BATTERY 3
FCBGA-932 Charger
PAGE 47
PAGE 7,8,9,10,11
VRAM
2 Channel and 4 sets Bluetooth
Interface
HUB
PAGE 20,21 PAGE 36
Power Interface &
TEMP. sensing circuit
266MHz 480MHz PAGE 46-54
(1.8V) USB 2.0 Port *3
Mini PCI PAGE 35
PAGE 29
Primary
LID/Kill Switch
RJ-45 LAN Power Buttom
PAGE 26 RTL8101L IDE HDD
PAGE 26 PCI BUS
33MHz (3.3V) ICH5 PAGE 33
PAGE 39
IEEE1394(BTO ) mBGA-460 Secondary
2 TSB43AB21A 2
PAGE 30 CD-ROM/DVD
PAGE 23,24,25 PAGE 33
Slot 0 CARDBAY
PAGE 28 A C-LINK
T7L65XB 27,28
PAGE AC97 CODEC Audio Amplifier
ALC 202 PAGE 31 TPA6011A4 32
PAGE
DIRECT BOARD
LPC BUS 33MHz (3.3V) PAGE 38
SD Conn
PAGE 28 MDC
Connector RJ-11
PAGE 36 PAGE 26
VR/CIR BOARD
PAGE 38
Super I/O Embedded
LPC47N227 Controller CIR
CIR
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REV B NS PC87591L Controller
PAGE 34 PAGE 37
PAGE 41 SW BOARD
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BIOS(1M)
FIR(BTO) Parallel Scan KB
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& I/O PORT
Compal Electronics, Inc.
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PAGE 35 PAGE 36 PAGE 37 PAGE 38
Title
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Block Digram
Size Document Number Rev
Custom 0.2
Date: Friday, August 08, 2003 Sheet 2 of 57
A B C D E
A B C D E
Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_VID 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VTT_GMCH +1.225V (Prescott) / +1.45V (Northwood) ON OFF OFF
+VGA_CORE 1.2V/1.5V switched power rail for VGA chip ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS AGP 4X/8X ON OFF OFF
+2.5V 2.5V power rail ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Table for AD channel
+3VALW 3.3V always on power rail ON ON ON*
+3V 3.3V power rail ON ON OFF Vcc 3.3V +/- 5%
+3VS 3.3V switched power rail ON OFF OFF Ra 100K +/- 5%
Board ID
+5VALW 5V always on power rail ON ON ON* Rb VAD_BID min VAD_BID typ VAD_BID max
+5V 5V power rail ON ON OFF 0 0 0 V 0 V 0 V
+5VS 5V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 2
+12VALW 12V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+RTCVCC RTC power ON ON ON 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 7 NC 2.500 V 3.300 V 3.300 V
External PCI Devices
Device IDSEL# REQ#/GN #
T Interrupts
VGA AD16 PIRQA
CardBus AD20 2 PIRQA/PIRQB/PIRQC/PIRQD Board ID PCB Revision
LAN AD17 3 PIRQF 0 0.1
Mini-PCI AD18 1/4 PIRQG/PI RQH 1
1394 AD16 0 PIRQE 2
SD AD22 PIRQA/PIRQB/PIRQC/PIRQD 3
3 4 3
5
6
EC SM Bus1 address EC SM Bus2 address 7
Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 110X b
EEPROM(24C16/02) 1010 000X b
(24C04) 1011 000Xb
ICH5 SM Bus address
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Device Address
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Clock Generator 1101 001Xb
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( ICS 952623)
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DDR DIMM0 1010 000Xb
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DDR DIMM2 1010 010Xb Compal Electronics, Inc.
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Title
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Notes
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Size Document Number Rev
B 0.2
LA-1911
Date: Friday, August 08, 2003 Sheet 3 of 57
A B C D E
5 4 3 2 1
+CPU_CORE
D D
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
C8
D7
D9
A8
B7
B9
JCPU1A
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
7 H_A#[3..31] H_D#[0..63] 7
H_A#3 K2 B21 H_D#0
H_A#4 K4 A#3 D#0 B22 H_D#1
H_A#5 L6 A#4 D#1 A23 H_D#2
H_A#6 K1 A#5 D#2 A25 H_D#3
H_A#7 L3 A#6 D#3 C21 H_D#4
H_A#8 M6 A#7 D#4 D22 H_D#5
H_A#9 L2 A#8 D#5 B24 H_D#6
H_A#10 M3 A#9 D#6 C23 H_D#7
H_A#11 M4 A#10 D#7 C24 H_D#8
H_A#12 N1 A#11 D#8 B25 H_D#9
H_A#13 M1 A#12 D#9 G22 H_D#10
H_A#14 N2 A#13 D#10 H21 H_D#11
H_A#15 N4 A#14 D#11 C26 H_D#12
H_A#16 N5 A#15 D#12 D23 H_D#13
H_A#17 T1 A#16 D#13 J21 H_D#14
H_A#18 R2 A#17 D#14 D25 H_D#15
H_A#19 P3 A#18 D#15 H22 H_D#16
H_A#20 P4 A#19 D#16 E24 H_D#17
H_A#21 R3 A#20 D#17 G23 H_D#18
H_A#22 T2 A#21 D#18 F23 H_D#19
H_A#23 U1 A#22 D#19 F24 H_D#20
H_A#24 P6 A#23 D#20 E25 H_D#21
H_A#25 U3 A#24 D#21 F26 H_D#22
H_A#26 T4 A#25 D#22 D26 H_D#23
H_A#27 V2 A#26 D#23 L21 H_D#24
H_A#28 R6 A#27 D#24 G26 H_D#25
H_A#29 W1 A#28 D#25 H24 H_D#26
H_A#30 T5 A#29 D#26 M21 H_D#27
H_A#31 U4 A#30 D#27 L22 H_D#28
V3 A#31 D#28 J24 H_D#29
C
W2
Y1
AB1
A#32
A#33
A#34
Prescott D#29
D#30
D#31
K23
H25
M23
H_D#30
H_D#31
H_D#32
C
A#35 D#32 N22 H_D#33
D#33 P21 H_D#34
7 H_REQ#[0..4] H_REQ#0 J1 D#34 M24 H_D#35
H_REQ#1 K5 REQ#0 D#35 N23 H_D#36
H_REQ#2 J4 REQ#1 D#36 M26 H_D#37
H_REQ#3 J3 REQ#2 D#37 N26 H_D#38
H_REQ#4 H3 REQ#3 D#38 N25 H_D#39
G1 REQ#4 D#39 R21 H_D#40
7 H_ADS# ADS# D#40 P24 H_D#41
D#41 R25 H_D#42
AC1 D#42 R24 H_D#43
V5 AP#0 D#43 T26 H_D#44
R25 62_0402_5% AA3 AP#1 D#44 T25 H_D#45
1 2 H_IERR# AC3 BINIT# D#45 T22 H_D#46
+CPU_CORE 1 2 IERR# D#46 T23 H_D#47
+CPU_CORE R35 200_0402_5% D#47 U26 H_D#48
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