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A B C D E
Compal Confidential ZZZ5
ZZZ1 ZZZ2 ZZZ3 ZZZ4
Model Name : Q1VZC
LA-8941P LS-8941P LS-8942P LS-8943P
File Name :LA-8941P PCB
DAZ@
DA2@ DA2@ DA2@ DA2@
1 1
BOM P/N:43
Compal Confidential
2 2
Q1VZC M/B Schematics Document
Intel Sandy Bridge ULV Processor + Panther Point PCH
3 2012-04-19 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/22 Deciphered Date 2012/11/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q1VZC M/B LA-8941P Schematic
Date: Friday, April 20, 2012 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential
Model Name : Q1VZC
File Name :LA-8941P
1
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 1
Intel BANK 0, 1, 2, 3 page 11,12
Dual Channel
Sandy Bridge ULV 1.5V DDRIII 1066/1333
Processor
eDP(UMA) BGA1023
17W
page 4~10
FDI x8 DMI x4
USB 2.0 USB 2.0 CMOS
CRT Conn HDMI Conn. LVDS/eDP Conn. CLK=100MHz CLK=100MHz conn x1(Option for USB3.0) conn x2 Camera
page 24 page 23 page 22 2.7GT/s 2.5GB/s x4 page 34 page 30 page 22
2
LVDS(UMA) USBx14 Port 1 Port 2,3 Port 10 2
3.3V 48MHz
Port 8
TMDS(UMA) Intel
RGB(UMA) LAN(GbE)/CardReader MINI Card
Broadcom
57785page WLAN
Panther Point-M 25 page 36
HD Audio
PCI-Express x 8 Port 3 Port 2
3.3V 24MHz
PCH (PCIE2.0 5GT/s) 100MHz
SPI
HDA Codec SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S)
ALC271X-VB6 100MHz
page 31 989pin BGA GEN3 Port 0
LS-8941P
page 13~21 SATA HDD LED/B
3
Conn. page 30 3
page 24
Int. Speaker SPI ROM x2 LPC BUS
page 31 page 13 CLK=33MHz LS-8942P
ENE IO/B
page 28
KB9012
RTC CKT. page 29
page 13 LS-8943P
HDD/B
page 24
Power On/Off CKT.
page 36 Touch Pad Int.KBD TPM
page 30 page 30 page 30
4 DC/DC Interface CKT. 4
page 33
Security Classification Compal Secret Data Compal Electronics, Inc.
Power Circuit DC/DC Issued Date 2011/11/22 Deciphered Date 2012/11/22 Title
Block Diagrams
page 34~43 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q1VZC M/B LA-8941P Schematic
Date: Friday, April 20, 2012 Sheet 2 of 45
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU ON OFF OFF Vcc 3.3V +/- 5%
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+VCCSUS3_3 +3VALW to +VCCSUS3_3 power rail for PCH (Short Jump) ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS +3VALW to +3VS power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VREF_SUS +5VALW to +5VREF_SUS power rail for PCH (Short resister) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS +5VALW to +5VS switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+RTCVCC RTC power ON ON ON
2
BOARD ID Table 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision BTO Option Table
0 0.1 BTO Item BOM Structure
1 0.2 Celeron 867 C867@
2 0.3 Pentium 977 P977@
3 1.0 Unpop @
4 eDP Panel EDP@
EC SM Bus1 address 5 LVDS Panel LVDS@
6 Connector CONN@
Device Address
Smart Battery 0001 011X b
7 USB3 Only USB3@
Deep S3 DS3@
PCH SM Bus address USB Port Table Normal S3 S3@
3 External Intel i5/i7 CPU only I57@
Device Address USB 2.0 USB 1.1 Port USB Port
ChannelA DIMM0 A0 1010 000X JDIMM1(STD) Celeron/Pentium/i3 CP3@
ChannelB DIMM0 B0 1010 010X JDIMM2(REV) 0 CPU only
UHCI0
1 USB 2.0(Options for USB3.0)
3 3
2 USB port(Left 2.0)
UHCI1
3 USB Port(Left 2.0)
EHCI1
4
UHCI2
5
USB 3.0 Port
6
UHCI3 1
7
2 USB Port(Right 3.0)
8 Mini Card(WLAN) XHCI
UHCI4 3
9
4
10 Camera
EHCI2 UHCI5
11
12
UHCI6
13
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/11/22 2012/11/22 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q1VZC M/B LA-8941P Schematic
Date: Friday, April 20, 2012 Sheet 3 of 45
A B C D E
A B C D E
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS_VTT
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1 - typical impedance = 14.5 mohms
24.9_0402_1%
UCPU1A
W=12mil L=500mil S=15mil
2
1 G3 PEG_COMP 1
PEG_ICOMPI G1
M2 PEG_ICOMPO G4
<15> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
P6
<15> DMI_CRX_PTX_N1 DMI_RX#[1]
P1
<15> DMI_CRX_PTX_N2 DMI_RX#[2]
P10 H22 C867@ Celeron 867 HR 1.3G SA00005BH40(S IC AV8062701148901 SR0FK J1 1.3G ABO!)
<15> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] J21
N3 PEG_RX#[1] B22
<15> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] P977@ Pentium 977 HR 1.4G SA00005BJ50(S IC AV8062701147701 SR0FB J1 1.4G ABO!)
P7 D21
<15> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
DMI
P3 A19 I2467@ i5-2467M HR 1.6G SA00004X010(S IC AV8062701047504 SR0D6 J1 1.6G ABO!)
<15> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
P11 D17
<15> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] B14 I2367@ i3-2367M HR 1.4G SA000051H60( S IC AV8062701047904 SR0CV J1 1.4G ABO! )
K1 PEG_RX#[6] D13
<15> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
M8 A11 C877@ Celeron 877 HR 1.4G SA00005QI00( S IC AV8062701148001 QB35 J1 1.4G BGA)
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
N4 B10
<15> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
R2 G8 P987@ Pentium 987 HR 1.5G SA00005QH00(S IC AV8062701147601 QB31 J1 1.5G BGA)
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8
K3 PEG_RX#[11] B6
<15> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] P967@ Pentium 967 HR 1.3G SA000051J40(S IC AV8062701147801 SR0FC J1 1.3G ABO!)
M7 H8
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
P4 E5 I2377@ i3-2377M HR 1.5G SA00005MX10(S IC AV8062701048004 QAXQ J1 1.5G BGA)
<15> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
T3 K7
<15> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
I3317@ i5-3317U CR 1.7G SA00005K650(S IC AV8063801058002 QC9E L1 1.7G BGA)
K22
PEG_RX[0] K19
PEG_RX[1] I3667@ i7-3667U CR 2G SA00005LA50(S IC AV8063801057405 QC9B L1 2G BGA 1023)
C21
U7 PEG_RX[2] D19
<15> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] I3217@ i3-3217U CR 1.8G SA00005L530(S IC AV8063801058400 QC56 L0 1.8G ABO!)
W11 C19
<15> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
<15> FDI_CTX_PRX_N2 W1 D16 I3427@ i5-3427U CR 1.8G SA00005L9A0(S IC AV8063801057801 SR0N7 L1 1.8G BGA)
AA6 FDI0_TX#[2] PEG_RX[5] C13
<15> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
2
<15> FDI_CTX_PRX_N4 W6 D12 I3517@ i7-3517U CR 1.9G SA00005K540(S IC AV8063801057605 QC9C L1 1.9G BGA) 2
V4 FDI1_TX#[0] PEG_RX[7] C11
PCI EXPRESS -- GRAPHICS
<15> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
<15> FDI_CTX_PRX_N6 Y2 C9
AC9 FDI1_TX#[2] PEG_RX[9] F8
<15> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
Intel(R) FDI
C8
PEG_RX[11] C5
U6 PEG_RX[12] H6
<15> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
W10 F6 UCPU1 UCPU1 UCPU1 UCPU1
<15> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
<15> FDI_CTX_PRX_P2 W3 K6
AA7 FDI0_TX[2] PEG_RX[15]
<15> FDI_CTX_PRX_P3 FDI0_TX[3]
<15> FDI_CTX_PRX_P4 W7 G22
T4 FDI1_TX[0] PEG_TX#[0] C23
<15> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
<15> FDI_CTX_PRX_P6 AA3 D23
AC8 FDI1_TX[2] PEG_TX#[2] F21 AV8062701147701 AV8062701047504 AV8062701047904 AV8062701148001
<15> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19 P977@ I2467@ I2367@ C877@
+1.05VS_VTT AA11 PEG_TX#[4] C17
<15> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
eDP_COMPIO and ICOMPO signals AC12 K15 SA00005BJ50 SA00004X010 SA000051H60 SA00005QI40
<15> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17
should be shorted near balls and U11 PEG_TX#[7] F14
routed with typical impedance <15> FDI_INT FDI_INT PEG_TX#[8] A15 UCPU1 UCPU1 UCPU1
PEG_TX#[9]
1
<25 mohms <15> FDI_LSYNC0
AA10
FDI0_LSYNC PEG_TX#[10]
J14
can't be left floating R2 AG8 H13
<15> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% M10
,even if disable eDP function... PEG_TX#[12] F10
PEG_TX#[13] D9
W=12mil L=500mil S=15mil
2
PEG_TX#[14] J4 AV8062701147601 AV8062701147801 AV8062701048004
EDP_COMP AF3 PEG_TX#[15] P987@ P967@ I2377@
AD2 eDP_COMPIO F22
EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23
3 eDP_HPD# PEG_TX[1] SA00005QH50 SA000051J40 SA00005MX60 HR(Sandy Bridge) 3
D24
PEG_TX[2] E21
AG4 PEG_TX[3] G19
<22> EDP_AUXN AF4 eDP_AUX# PEG_TX[4] B18
<22> EDP_AUXP eDP_AUX PEG_TX[5] K17
eDP PEG_TX[6] G17 UCPU1 UCPU1 UCPU1
+1.05VS_VTT AC3 PEG_TX[7] E14
<22> EDP_TXN0 eDP_TX#[0] PEG_TX[8]
AC4 C15
<22> EDP_TXN1 eDP_TX#[1] PEG_TX[9]
AE11 K13
eDP_TX#[2] PEG_TX[10]
1
AE7 G13
R3 eDP_TX#[3] PEG_TX[11] K10
1K_0402_5% AC1 PEG_TX[12] G10 AV8063801058002 AV8063801057405 AV8063801058401
<22> EDP_TXP0 eDP_TX[0] PEG_TX[13]
EDP@ AA4 D8 I3317@ I3667@ I3217@
<22> EDP_TXP1 eDP_TX[1] PEG_TX[14]
AE10 K4
2
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3] SA00005K6B0 SA00005LAA0 SA00005L5C0
EDP_HPD#
<22> EDP_HPD#
IVY-BRIDGE_BGA1023 UCPU1 UCPU1
C867@
AV8063801057801 AV8063801057605
I3427@ I3517@
SA00005L9B0 SA00005K5B0 CR(Ivy Bridge)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/11/22 2012/11/22 Title
Issued Date Deciphered Date PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q1VZC M/B LA-8941P Schematic
Date: Friday, April 20, 2012 Sheet 4 of 45
A B C D E
A B C D E
0921 LVDS@->@ +1.05VS_VTT
CLK_CPU_DPLL# R4 2 LVDS@ 1 1K_0402_5%
CLK_CPU_DPLL R5 2 LVDS@ 1 1K_0402_5%
Checklist1.5 P.67 Graphis Disable Guide
eDP disable:
DPLL_REF_SSCLK PD 1K_5% to GND
1 DPLL_REF_SSCLK# PU 1K_5% to +1.05VS_VTT 1
UCPU1B
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